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參數(shù)資料
| 型號(hào)： | 80C03 |
| 廠商： | LSI Corporation |
| 英文描述： | AutoDUPLEX CMOS Ethernet Data Link Controller(AutoDUPLEX CMOS 以太網(wǎng)數(shù)據(jù)鏈路控制器) |
| 中文描述： | AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制（AutoDUPLEX的CMOS以太網(wǎng)數(shù)據(jù)鏈路控制器） |
| 文件頁(yè)數(shù)： | 10/19頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | 80C03 |
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80C03
4-10
MD400121/C
Transmit Control Register
Available in 80C03 mode only. Allows for control of trans-
mit Collision Counter, total Collision Counter, SQE func-
tion, carrier oss on ransmit reporting, Multi-cast hash ilter
reception of runt frames. Set to all ‘0’s after reset.
Multicast Mode
There is a 64 bit multicast address filter register on 80C03
which can accessed as shown n table (page 9). When the
SEEQ 80C03 is programmed to receive multicast frames
(match mode 3), after computing the CRC on the address
field of the receiving frame (first 6 bytes), t will ndex to the
multicast address filter register depending on bits 0 to 5 of
the CRC. If the corresponding bit is a ‘1’ it will receive the
frame, otherwise it will discard the frame.
SQE Status Bit
After transmitting a frame if 80C03 does not receive a
collision with n a 4.0
μ
s period this bit will be set. Once set
this will stay set until cleared. This can read and cleared
as explained in the register section.
Collision Count Registers
There are two 16 bit read only collision count registers
which are cleared on reset. One counts the collisions on
transmission and the other counts all the collisions except
the ones in the SQE_WINDOW. The transmit collision
counter is eleven bits wide. Bits 15 to 11 of this register
7
6
5
3
2 1
4
X
X
0
Bit 0 = ‘1’ Enables Transmit
Collision Counter
Bit 0 = ‘0’ Clears Transmit
Collision Counter
Bit 1 = ‘1’ Enables
Collision Counter
Bit 1 = ‘0’ Clears
Collision Counter
Bit 2 = ‘1’ Enables
sqe Function
Bit 2 = ‘0’ Clears
sqe Flag
Bit 3 = ‘1’ Enables
Hash Filter for Multicast
Bit 3 = ‘0’ Disables
Hash Filter for Multicast
Bit 4 = ‘1’ Disables
The Reception of Frames
Shorter Than 13 Bytes
Bit 5 = ‘1’ Enables
txen_no_carrier Function
Bit 5 = ‘0’ Clears
txen_no_carrier Flag
indicates the attempt counter used in SEEQ for collision
back off. These can be read and cleared as described in
register section.
TxEN_no_carrier
When txen goes from 1 to 0, if there is no carrier this bit is
set. Once set this will stay set until cleared. These can be
read and cleared as described in register section.
Test Mode
Bits 7 and 4 of the Transmit command register are used for
testing purposes only. For normal operation these bits
should be set to ‘0’.
Tx-Rx Configuration Register
Available n 80C03 mode only. Allows or control of various
transmit and receive features. Set to all 0’s after reset.
Group Address Mode
In this mode the ast 4 bits of the serial receive data stream
for the destination address are masked out in address
comparison. This means that when the destination ad-
dress is compared against the value programmed in the
station address register that the packet will not be rejected
due to incorrect address even its last 4 bits did not match.
7
6
5
3
2 1
4
0
Bit 0 = ‘1’ Enables Group
Address Mode
Bit 1 = ‘1’ Enables Transmit
Packet Autopad Mode
Bit 2 = ‘1’ Enables Transmit No
Preamble Mode
Bit 3 = ‘1’ Enables Receive Own
Traansmit Disable Mode
Bit 4 = ‘1’ Enables Transmit No
CRC Mode
Bit 5 = ‘1’ Enables Full Duplex
Mode
Bit 6 = ‘1’ Enables Receive CRC
Mode
Bit 7 = ‘1’ Enables Fast Receive
Discard Mode
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