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參數(shù)資料
| 型號(hào)： | 78Q2133R/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 MDIX 3.3V IND 32-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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DS_21x3_001
78Q2123/78Q2133 Data Sheet
Rev. 1.6
17
cleared by a read operation.
1.0
EXTD
R
1
Extended Capability: Reads ’1’ to indicate the
78Q2123/78Q2133 provide an extended register set (MR2
and beyond).
3.3
MR2: PHY Identifier Register 1
Bit
Symbol
Type
Value
Description
2.15:0
OUI [23:6]
R
000Eh
Organizationally Unique Identifier: This value is 00-C0-39 for
Teridian Semiconductor Corporation. This register contains the
first 16-bits of the identifier.
3.4
MR3: PHY Identifier Register 2
Bit
Symbol
Type
Value
Description
3.15:10
OUI [5:0]
R
1Ch
Organizationally Unique Identifier: Remaining 6 bits of the
OUI.
3.9:4
MN
R
23h
Model Number: The last 2 digits of the model number
78Q2123 are encoded into the 6 bits for both 78Q2123 and
78Q2133.
3.3:0
RN
R
07h
Revision Number: The value ‘0111’ corresponds to the
seventh revision of the silicon.
3.5
MR4: Auto-Negotiation Advertisement Register
Bit
Symbol
Type
Default
Description
4.15
NP
R
0
Next Page: Not supported. Reads logic zero.
4.14
RSVD
R
0
Reserved
4.13
RF
R/W
0
Remote Fault: Setting this bit to ‘1’ allows the device to
indicate to the link partner a Remote Fault Condition.
4.12
A7
R
0
Reserved.
4.11
A6
R/W
0
Asymmetric PAUSE Support Indication for Full Duplex Links.
Default is 0 indicating not supported. If the MAC supports
Asymmetric PAUSE, this bit can be written as 1. Writing to this
register has no effect until auto-negotiation is re-initiated.
4.10
A5
R
0
PAUSE Support Indication for Full Duplex Links. Default is 0
indicating not supported. If the MAC supports PAUSE, this bit
can be written as 1. Writing to this register has no effect until
auto-negotiation is re-initiated
4.9
A4
R
0
100BASE-T4: The 78Q2123/78Q2133 do not support
100BASE-T4 operation.
4.8
A3
R/W
(1)
100BASE-TX Full Duplex: If the MR1.14 bit is ‘1’, this bit will
be set to ‘1’ upon reset and will be writeable. Otherwise, this
bit cannot be set to ‘1’ by the management.
4.7
A2
R/W
(1)
100BASE-TX: If the MR1.13 bit is ‘1’, this bit will be set to ‘1’
upon reset and will be writeable. Otherwise, this bit cannot be
set to ‘1’ by the management.
4.6
A1
R/W
(1)
10BASE-T Full Duplex: If the MR1.12 bit is ‘1’, this bit will be
set to ‘1’ upon reset and will be writeable. Otherwise, this bit
cannot be set to ‘1’ by the management.
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