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參數(shù)資料
| 型號： | 78Q2133R/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 MDIX 3.3V IND 32-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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78Q2123/78Q2133 Data Sheet
DS_21x3_001
20
Rev. 1.6
3.9
MR17: Interrupt Control/Status Register
The Interrupt Control/Status Register provides the means for controlling and observing the events, which
trigger an interrupt on the INTR pin. This register can also be used in a polling mode via the MII Serial
Interface as a means to observe key events within the PHY via one register address. Bits 0 through 7 are
status bits, which are each set to logic one based upon an event. These bits are cleared after the register
is read. Bits 8 through 15 of this register, when set to logic one, enable their corresponding bit in the
lower byte to signal an interrupt on the INTR pin. The assertion level of this interrupt signal output on the
INTR pin can be set via the MR16.14 (INPOL) bit.
Bit
Symbol
Type
Default
Description
17.15
JABBER_IE
R/W
0
Jabber Interrupt Enable
17.14
RXER_IE
R/W
0
Receive Error Interrupt Enable
17.13
PRX_IE
R/W
0
Page Received Interrupt Enable
17.12
PDF_IE
R/W
0
Parallel Detect Fault Interrupt Enable
17.11
LP-ACK_IE
R/W
0
Link Partner Acknowledge Interrupt Enable
17.10
LS-CHG_IE
R/W
0
Link Status Change Interrupt Enable
17.9
RFAULT_IE
R/W
0
Remote Fault Interrupt Enable
17.8
ANEG-
COMP_IE
R/W
0
Auto-Negotiation Complete Interrupt Enable
17.7
JAB_INT
RC
0
Jabber Interrupt: This bit is set high when a Jabber
event is detected by the 10Base-T circuitry.
17.6
RXER_INT
RC
0
Receive Error Interrupt: This bit is set high when the
RX_ER signal transitions high.
17.5
PRX_INT
RC
0
Page Received Interrupt: This bit is set high when a new
page has been received from the link partner during
auto-negotiation.
17.4
PDF_INT
RC
0
Parallel Detect Fault Interrupt: This bit is set high by the
auto-negotiation logic when a parallel detect fault
condition is indicated.
17.3
LP-ACK_INT
RC
0
Link Partner Acknowledge Interrupt: This bit is set high
by the auto-negotiation logic when FLP bursts are
received with the acknowledge bit set.
17.2
LS-CHG_INT
RC
0
Link Status Change Interrupt: This bit is set when the
link transitions from an OK status to a FAIL status.
17.1
RFAULT_INT
RC
0
Remote Fault Interrupt: This bit is set when a remote
fault condition has been indicated by the link partner.
17.0
ANEG-
COMP_INT
RC
0
Auto-Negotiation Complete Interrupt: This bit is set by
the auto-negotiation logic upon successful completion of
auto-negotiation.
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