參數(shù)資料
型號： 78Q2133R/F
廠商： Maxim Integrated Products
文件頁數(shù)： 2/38頁
文件大?。?/td> 0K
描述： TXRX 10/100 MDIX 3.3V IND 32-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： PHY 收發(fā)器
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： IEEE 802
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
78Q2123/78Q2133 Data Sheet
DS_21x3_001
10
Rev. 1.6
1.6
Additional Features
1.6.1
LED Indicators
There are two LED pins that can be used to indicate various states of operation of the
78Q2123/78Q2133. The function of these pins is programmable via the MR23 register as shown in the
table below:
LED State Indication
0
1 = Link OK (Default LED0)
1
1 = RX or TX Activity (Default LED1)
2
1 = TX Activity
3
1 = RX Activity
4
1 = Collision
5
1 = 100 BASE-TX mode
6
1 = 10 BASE-T mode
7
1 = Full Duplex
8
1= Link OK & Blink = RX or TX Activity
The default status of these LEDs are “Link OK” for LED0 and “RX or TX Activity” for LED1.
1.6.2
Interrupt Pin
The 78Q2123 and 78Q2133 have an Interrupt pin (INTR) that is asserted whenever any of the eight
interrupt bits of MR17.7:0 are set. These interrupt bits can be disabled via the MR17.15:8 Interrupt
Enable bits. The Interrupt Polarity bit, MR16.14, controls the active level of the INTR pin. When the INTR
pin is not asserted, the pin is held in a high impedance state. An external pull-up or pull-down resistor may
be required for use with the INTR pin.
1.6.3
Automatic MDI/ MDI-X Configuration
The 78Q2123 and 78Q2133 implement the automatic MDI/MDI-X configuration detailed in IEEE-802.3
2002. This function eliminates the need for cross over cables when connecting to another device. When
auto-switching is enabled, the 78Q2123/78Q2133 will attempt to detect activity on its given configuration.
If no activity is seen for 60 ms, the device will switch to the other configuration depending on a random
number sequence. The initial seed of the random number generator can be set via MR24.3:0. In
addition, the part includes an asynchronous MDIX reset that varies from 1.29 seconds to 1.57 seconds to
ensure lock step will not occur between two devices.
The 78Q2123 and 78Q2133 will also allow for auto-switching while the part is not in auto-negotiation
mode. The IEEE 802.3 specification will not work in this case if the other device is in auto-negotiation
mode. The 78Q2123 and 78Q2133 default to auto MDIX enabled with parallel detection. Register bits
MR24.6 and MR24.7 are both defaulted to 1. The 78Q2123 and 78Q2133 will resolve the proper
configuration within 5 seconds.
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