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參數(shù)資料
| 型號： | 78Q2133R/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX 10/100 MDIX 3.3V IND 32-QFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | PHY 收發(fā)器 |
| 驅動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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DS_21x3_001
78Q2123/78Q2133 Data Sheet
Rev. 1.6
15
3.1
MR0: Control Register
Bit
Symbol
Type
Default
Description
0.15
RESET
R/WC
0
Reset: Setting this bit to ‘1’ resets the device and sets all
registers to their default states. This bit is self-clearing.
0.14
LOOPBK
R/W
0
Loopback: When this bit is set to ‘1’, input data at TXD[3:0] is
output at RXD[3:0]. No transmission of data on the network
medium occurs and receive data on the network medium is
ignored. By default, the loopback signal path encompasses
most of the digital functional blocks. This bit allows for
diagnostic testing.
0.13
SPEEDSL
R/W
1
Speed Selection: This bit determines the speed of operation
of the 78Q2123/78Q2133. Setting this bit to ‘1’ indicates
100Base-TX operation and a ‘0’ indicates 10Base-T mode.
This bit will default to a ‘1’ upon reset. When auto-negotiation
is enabled, this bit will not be writable and will have no effect
on the 78Q2123/78Q2133. If auto-negotiation is not enabled,
this bit may be written to force manual configuration.
0.12
ANEGEN
R/W
1
Auto-Negotiation Enable: The auto-negotiation process is
enabled by setting this bit to ‘1’. This bit will default to ‘1’. If
this bit is cleared to ‘0’, manual speed and duplex mode
selection is accomplished through bits 0.13 (SPEEDSL) and
0.8 (DUPLEX) of the Control Register.
0.11
PWRDN
R/W
0
Power-Down: The device may be placed in a low power
consumption state by setting this bit to ‘1’. While in the power-
down state, the device will still respond to management
transactions.
0.10
ISO
R/W
0
Isolate: When set to ‘1’, the device will present a high-
impedance on its MII output pins. This allows for multiple
PHY’s to be attached to the same MII interface. When the
device is isolated, it still responds to management
transactions.
0.9
RANEG
R/WC
0
Restart Auto-Negotiation: Normally, the Auto-Negotiation
process is started at power up. The process can be restarted
by setting this bit to ‘1’. This bit is self-clearing.
0.8
DUPLEX
R/W
1
Duplex Mode: This bit determines whether the device
supports full- duplex or half-duplex. A ‘1’ indicates full-duplex
operation and a ‘0’ indicates half-duplex. This bit will default
to ‘1’ upon reset. When auto-negotiation is enabled, this bit
will not be writable and will have no effect on the
78Q2123/78Q2133. If auto-negotiation is not enabled, this bit
may be written to force manual configuration.
0.7
COLT
R/W
0
Collision Test: When this bit is set to ‘1’, the device will assert
the COL signal in response to the assertion of the TX_EN
signal. Collision test is disabled if the PCSBP bit, MR16.1, is
high. Collision test can be activated regardless of the duplex
mode of operation.
0.6:0
RSVD
R
0
Reserved
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