2006 Teridian Semiconductor Corporation Rev. 2" />
參數(shù)資料
型號(hào)： 78P2352-IGTR/F
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 5/42頁(yè)
文件大?。?/td> 0K
描述： IC LIU SDH SONET 2CH 128-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： E4，OC-3，STM1-E
電源電壓： 3.15 V ~ 3.45 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP-EP（14x14）
包裝： 帶卷 (TR)
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 13 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (CONTINUED)
ADDRESS N-1: SIGNAL CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
TCMIINV
R/W
0
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIxP/N.
For debug use only.
0: Normal
1: Invert
6
RCMIINV
R/W
0
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXxP/N. For
debug use only.
0: Normal
1: Invert
5
LOLOR
R/W
0
Receive Loss of Lock/Signal Override:
When high, the RXLOL and RXLOS signals will always remain low.
0: Normal
1: Forces LOS and LOL outputs to be low and resets counters
NOTE: For reliable operation of the Rx LOL detection circuitry, one must
manually reset the LOL counter by toggling this bit upon power-up or
initialization.
4
RLBK
R/W
0
3
LLBK
R/W
0
Analog Loopback Selection:
RLBK LLBK
0
Normal operation
1
0
Remote Loopback Enable: Recovered receive data
is looped back to the transmit driver for retransmission.
0
1
Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
2
RCLKP
R/W
0
Receive Clock Inversion Select:
This bit will invert the receive output clock.
0: Normal. Data clocked out on falling edge of receive clock.
1: Invert. Data clocked out on the rising edge of receive clock.
1
TCLKP
R/W
0
Transmit Clock Inversion Select:
This bit will invert the transmit input system clock.
0: Normal. Data is clocked in on rising edge of the transmit clock.
1: Invert. Data is clocked in on the falling edge of the transmit clock.
0
FRST
R/W
0
FIFO Reset:
0: Normal operation
1: Reset FIFO pointers to default locations.
This reset should be initiated anytime the transmitter or IC powers up to
ensure the FIFO is centered after internal VCO clocks and external
transmit clocks are stable.
*Not required for Plesiochronous Serial Mode
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