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參數(shù)資料
| 型號： | 78P2352-IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SDH SONET 2CH 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 18 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION (CONTINUED)
REFERENCE AND STATUS PINS
Note: The LOSx, LOLx, and INTxXxB pins are configurable at final test (default open-drain outputs). If CMOS
level outputs are required, please refer to alternate 70Pxxxx ordering numbers at the end of the data sheet.
NAME
PIN
TYPE
DESCRIPTION
CKREFP
CKREFN
111
110
PI/
CI
Reference Clock Input:
A required reference clock input used for clock/data recovery and frequency
synthesizer. Options include :
139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock
input at CKREFP/N
17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) single-
ended CMOS clock input at CKREFP. Tie CKREFN to ground when
unused.
LOS1
LOS2
80
19
OD/
CO
Receive Loss of Signal (active-high):
See Receiver Loss of Signal description for conditions.
LOL1
LOL2
79
20
OD/
CO
Receive Loss of Lock (active-high):
This condition is met when the recovered clock frequency differs from the
reference clock frequency by more than +/- 100ppm.
INTTX1B
INTTX2B
88
9
OD/
CO
Transmitter Fault Interrupt Flag (active low):
When a transmitter error event occurs (as defined in the Interrupt Control
Register Description), the INTTXxB pin will change state to indicate an
interrupt. The interrupt is cleared by a read to the STAT Register, an issue
of a FRSTx FIFO reset pulse (if the FIERRx signal caused the interrupt), or
when the TXLOL register bit transitions from high to low.
Note: The default interrupt condition is a loss of lock in the transmitter CDR.
INTRX1B
INTRX2B
70
27
OD/
CO
Receiver Fault Interrupt Flag (active low):
Reserved for future use.
PORB
83
A
Power-On Reset (active low):
See Power-On Reset description on use of this pin.
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