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參數(shù)資料
| 型號(hào)： | 78P2352-IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/42頁 |
| 文件大小： | 0K |
| 描述： | IC LIU SDH SONET 2CH 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 12 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
REGISTER DESCRIPTION (CONTINUED)
PORT-SPECIFIC REGISTERS
For PA[3:0] = 1-2 = N only. Accessing a register with port address greater than 2 constitutes an invalid command,
and the read/write operation will be ignored.
ADDRESS N-0: MODE CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7
PDTX
R/W
0
Transmitter Power-Down:
0 : Normal Operation
1 : Power-Down. CMI Transmit output is tri-stated.
6
PDRX
R/W
0
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
5
PMODE
R/W
X
Parallel Mode Interface Selection:
When PAR=0, PMODE is invalid and defaults to logic ‘1’;
When PAR=1, (Master Control Register: bit 5), PMODE selects the
source of the transmit parallel clock, either taken from the framer
externally or generated internally. Default value is determined by
CKMODE pin setting upon power up or reset.
0: Slave Timing. PIxCK clock input to the transmitter
1: Master Timing. PTOxCK clock output from the transmitter
4
SMOD[1]
R/W
X
3
SMOD[0]
R/W
X
Serial Mode Interface Selection:
When PAR=0 (Master Control Register: bit 5), SMOD[1:0] configures
the transmitter’s system interface. Default values determined by
CKMODE pin setting upon power up or reset.
SMOD[1] SMOD[0]
0
Synchronous clock and data are passed through a
FIFO. The CDR is bypassed.
1
0
Synchronous data is passed through the CDR and
then through the FIFO.
0
1
Plesiochronous data is passed through the CDR to
recover a clock. FIFO is bypassed because the
data is not synchronous with the reference clock.
1
Loop Timing Mode Enable: The recovered receive
clock is used as the reference for the transmit DLL
and FIFO.
When PAR=1 (Master Control Regsiter: bit 5), setting SMOD[1:0] = 11
will enable Loop Timing Mode. Default values are determined by
CKMODE pin setting upon power up or reset as follows:
CKMODE Low
SMOD[1:0] default = 00 (no effect)
CKMODE Float
SMOD[1:0] default = 11 (loop-timing enable)
CKMODE High
SMOD[1:0] default = 01 (no effect)
2
MON
R/W
0
Receive Monitor Mode Enable:
0: Normal Operation
1: Adds 20dB of flat gain to the receive signal before equalization
NOTE: Monitor mode is only available in CMI mode.
1:0
--
R/W
00
Reserved
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