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參數(shù)資料
| 型號： | 78P2352-IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SDH SONET 2CH 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Page: 19 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION (CONTINUED)
CONTROL PINS
NAME
PIN
TYPE
DESCRIPTION
FRST
78
CIT
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRSTx will resume FIFO operation.
Low: Channel 1 FRST assertion
Float: Normal operation
High: Channel 2 FRST assertion
Because the internal VCO clock and off-chip transmit clocks may not be
stable during transmit power-up, it is recommended to always reset the FIFOs
after powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
LPBKx
17, 18
CIT
Analog Loopback Selection:
Low: Normal operation
Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
CKMODE
15
CIT
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
Low: Parallel transmit clock is input to the 78P2352.
Float: Parallel transmit clock is input to the 78P2352. Loop-timing
mode enabled.
High: Parallel transmit clock is output from the 78P2352
In SERIAL mode (SDI_PAR low):
Low: Reference clock is synchronous to transmit clock and data.
Data is clocked in with SIxCKP/N and passed through a FIFO
Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
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