
7751 Group User’s Manual
INT E R R UPT S
4–20
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4.10 External interrupts (INT
i
interrupt)
An external interrupt request occurs by input signals to the INT
i
(i = 0 to 2) pin. The occurrence factor of
interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits
5 and 4 at addresses 7D
16
to 7F
16
) shown in Figure 4.10.1. Table 4.10.1 lists the occurrence factor of INT
i
interrupt request.
When using P6
2
/INT
0
to P6
4
/INT
2
pins as input pins of external interrupts, set the corresponding bits at
address 10
16
(port P6 direction register) to “0.” (Refer to Figure 4.10.2.)
The signals input to the INT
i
pin require “H” or “L” level width of 250 ns or more independent of the f(X
IN
).
Additionally, even when using the pins P6
2
/INT
0
to P6
4
/INT
2
as the input pins of external interrupt, the user
can obtain the pin’s state by reading bits 2 to 4 at address E
16
(port P6 register).
Note:
When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request,
make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising
or “H” level as that, make sure that the input signal is held “H” for 250 ns or more.
4.10 External interrupts (INT
i
interrupt)
Table 4.10.1 Occurrence factor of INT
i
interrupt request
b4
0
1
0
1
1
Interrupt request occurs while the INT
i
pin level is “L” (level sense).
b5
0
0
1
INT
i
interrupt request occurrence factor
___
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The INT
i
interrupt request occurs by always detecting the INT
i
pin’s state. Accordingly, when the user does
not use the INT
i
interrupt, set the INT
i
interrupt’s priority level to level 0.
Interrupt request occurs at falling of the signal input to the INT
i
pin (edge sense).
Interrupt request occurs at rising of the signal input to the INT
i
pin (edge sense).
Interrupt request occurs while the INT
i
pin level is “H” (level sense).