
APPE NDIX
7751 Group User’s Manual
20–7
Appendix 2. Memory assignment in SFR area
5C
16
5D
16
5E
16
5F
16
Timer B1 mode register
Timer B2 mode register
0
40
16
41
16
42
16
43
16
44
16
45
16
46
16
47
16
48
16
49
16
4A
16
50
16
51
16
52
16
53
16
54
16
55
16
56
16
57
16
58
16
59
16
5A
16
5B
16
4B
16
4C
16
4D
16
4E
16
4F
16
WO
8
8
8
8
8
8
8
8
8
8
8
8
8
8
RW
8
8
b7
b0
RW
RW
RW
RW
RW
RW
RW
WO
RW
00
16
00
16
00
16
00
16
00
16
00
16
b7
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
WO
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
0
0
0
0
0
0
: It is possible to read the bit state at reading. The written value becomes valid data.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.
RW
RO
WO
Access characteristics
: “0” immediately after a reset.
: “1” immediately after a reset.
:
Undefined immediately after
a reset.
0
1
: Always “0” at reading
0
0
: Always undefined at reading
: “0” immediately after a reset. Fix this bit to “0.”
State immediately after a reset
Register name
Address
Access characteristics
State immediately after a reset
Timer B2 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Processor mode register 0
Processor mode register 1
One-shot start register
Timer A0 register
Up-down register
Timer A1 register
Count start register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer A0 mode register
8
8
8
8
8
The access characteristics at addresses 46
16
to 4F
16
varies according to Timer A’s operating mode.
(Refer to
“Chapter 5. TIMER A.”
)
8
The access characteristics at addresses 50
16
to 55
16
varies according to Timer B’s operating mode.
(Refer to
“Chapter 6. TIMER B.”
)
8
The access characteristics of bit 5 at addresses 5B
16
to 5D
16
varies according to Timer B’s operating
mode. (Refer to
“Chapter 6. TIMER B.”
)
8
The access characteristics of bit 1 at address 5E
16
and its state immediately after a reset vary according
to the voltage level supplied to the CNV
SS
pin. (Refer to section
“2.5 Processor modes.”
)