
7751 Group User’s Manual
4–7
INT E R R UPT S
4.3 Interrupt control
Fig. 4.3.2 Structure of interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 70
16
to 7C
16
)
Bit
7 to 4
Interrupt request bit
2
1
0
Bit name
At reset
0
RW
Functions
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Low level
High level
b2 b1 b0
0 : No interrupt request
1 : Interrupt request
Interrupt priority level select bits
3
RW
RW
RW
RW
–
Undefined
0
0
0
Nothing is assigned.
b7
b6
b5
b4
b3
b2
b1
b0
INT
0
to INT
2
interrupt control registers (Addresses 7D
16
to 7F
16
)
Bit
4
Interrupt request bit
(Note)
2
1
0
Bit name
At reset
0
RW
Functions
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Low level
High level
b2 b1 b0
0 : No interrupt request
1 : Interrupt request
0 : Edge sense
1 : Level sense
Note:
The INT
0
to INT
2
interrupt request bits are invalid when selecting the level sense.
Interrupt priority level select bits
3
7, 6
5
RW
RW
RW
RW
RW
RW
–
0
0
Undefined
0
0
0
Polarity select bit
0 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
“L” level for level sense and at
rising edge for edge sense.
Level sense/Edge sense select
bit
Nothing is assigned.