
7751 Group User’s Manual
8–10
A-D CONVE R T E R
8.3 A-D conversion method (successive approximation conversion method)
8.3 A-D conversion method (successive approximation conversion method)
The A-D converter compares the comparison voltage (V
ref
), which is internally generated according to the
contents of the successive approximation register, with the analog input voltage (V
IN
), which is input from
the analog input pin (AN
i
). By reflecting the comparison result on the successive approximation register, V
IN
is converted into a digital value. When a trigger is generated, the A-D converter performs the following
processing:
Determining bit 9 of the successive approximation register
The A-D converter compares V
ref
with V
IN
. At this point, the contents of the successive approximation
register are “1000000000
2
” (initial value).
Bit 9 of the successive approximation register changes according to the comparison result as follows:
When V
ref
< V
IN
, bit 9 = “1”
When V
ref
> V
IN
, bit 9 = “0”
Determining bit 8 of the successive approximation register
After setting bit 8 of the successive approximation register to “1,” the A-D converter compares V
ref
with V
IN
. Bit 8 changes according to the comparison result as follows:
When V
ref
< V
IN
, bit 8 = “1”
When V
ref
> V
IN
, bit 8 = “0”
Determining bits 7 to 0 of the successive approximation register
Operation in
are performed for bits 7 to 0 in the 10-bit mode.
Operation in
are performed for bits 7 to 2 in the 8-bit mode.
When the LSB is determined, the contents (conversion result) of the successive approximation register
are transferred to the A-D register i.
The comparison voltage (V
ref
) is generated according to the latest contents of the successive approximation
register. Table 8.3.1 lists the relationship between the successive approximation register’s contents and V
ref
.
Table 8.3.2 and Table 8.3.3 list changes of the successive approximation register and V
ref
during the A-D
conversion. Figure 8.3.1 shows the ideal A-D conversion characteristics in the 10-bit mode.
Table 8.3.1 Relationship between successive approximation register’s contents and V
ref
Successive approximation register’s contents: n
0
V
REF
8
1024
1 to 1023
(n – 0.5)
V
ref
(V)
0
V
REF
8
: Reference voltage