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參數(shù)資料
| 型號： | 74HC7404N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 5-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 64 X 5 OTHER FIFO, 98 ns, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 131K |
| 代理商： | 74HC7404N |
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September 1993
27
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Note to
Fig.24
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
After a MR pulse has been applied FIFO
A
and FIFO
B
are empty. The DOR flags of FIFO
A
and FIFO
B
go LOW due to no
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SO
B
is held HIGH and two SI
A
pulses are applied (1). These pulses allow two data words to ripple through to the output stage
of FIFO
A
and to the input stage of FIFO
B
(2). When data arrives at the output of FIFO
B
, a DOR
B
pulse is generated (3).
When SO
B
goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DOR
B
goes
HIGH (4).
Fig.24 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
handbook, full pagewidth
DORB OUTPUT
DIRB OUTPUT
DORA OUTPUT
DIRA OUTPUT
QnB
QnA OUTPUT
SIA
DnA
MR INPUT
SOB
sequence 1
sequence 2
sequence 3
sequence 4
sequence 5
sequence 6
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
MGA687
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