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參數(shù)資料
| 型號(hào)： | 74HC7404N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 5-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 64 X 5 OTHER FIFO, 98 ns, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 131K |
| 代理商： | 74HC7404N |
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September 1993
25
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Notes to
Fig.22
1.
2.
3.
FIFO
A
and FIFO
B
initially empty, SO
A
held HIGH in anticipation of data
Load one word into FIFO
A
; SI pulse applied, results in DIR pulse
Data-out
A
/data-in
B
transition; valid data arrives at FIFO
A
output stage after a specified delay of the DOR flag,
meeting data input set-up requirements of FIFO
B
DOR
A
and SI
B
pulse HIGH; (ripple through delay after SI
A
LOW) data is unloaded from FIFO
A
as a result of the data
output ready pulse, data is shifted into FIFO
B
DIR
B
and SO
A
go LOW; flag indicates input stage of FIFO
B
is busy, shift-out of FIFO
A
is complete
DIR
B
and SO
A
go HIGH automatically; the input stage of FIFO
B
is again able to receive data, SO is held HIGH in
anticipation of additional data
DOR
B
goes HIGH; (ripple through delay after SI
B
LOW) valid data is present one propagation delay later at the FIFO
B
output stage.
4.
5.
6.
7.
Fig.22 FIFO to FIFO communication; input timing under empty condition.
handbook, full pagewidth
VM
(1)
DORB
SIA
VM
(1)
MGA666
5
6
DIR
QnA
nB
D
SOA
DIRB
DORASIB
VM
(1)
2
ripple through
delay
VM
(1)
VM
(1)
1
4
ripple through
delay
3
nB
Q
7
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