參數(shù)資料
型號： 74HC7404N
廠商： NXP SEMICONDUCTORS
元件分類： FIFO
英文描述： 5-Bit x 64-word FIFO register; 3-state
中文描述： 64 X 5 OTHER FIFO, 98 ns, PDIP18
封裝： PLASTIC, DIP-18
文件頁數(shù)： 13/28頁
文件大小： 131K
代理商： 74HC7404N
September 1993
13
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
With FIFO full; SI held HIGH in anticipation of empty location
Notes to
Fig.8
1.
2.
3.
4.
5.
FIFO is initially full, shift-in is held HIGH
SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
handbook, full pagewidth
SI INPUT
MGA660
3
4
DIR OUTPUT
VM
(1)
2
bubble - up
delay
VM
(1)
5
SO INPUT
tPLH
VM
(1)
1
tW
(1) HC
:
V
M
= 50%; V
I
= GND to V
.
V
M
= 1.3 V; V
I
= GND to 3 V.
HCT :
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