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參數資料
| 型號： | 74HC7404N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 5-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 64 X 5 OTHER FIFO, 98 ns, PDIP18 |
| 封裝： | PLASTIC, DIP-18 |
| 文件頁數： | 23/28頁 |
| 文件大?。?/td> | 131K |
| 代理商： | 74HC7404N |
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September 1993
23
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Note to
Fig.20
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in
cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are
started (see Fig.8 and Fig.10).
Expanded format
Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 5 bits. Figure 22 shows the signals on the
nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a ripple through delay,
data arrives at the output of FIFO
A
. Due to SO
A
being HIGH, a DOR
A
pulse is generated. The requirements of SI
B
and
D
nB
are satisfied by the DOR
A
pulse width and the timing between the rising edge of DOR
A
and Q
nA
. After a second ripple
through delay, data arrives at the output of FIFO
B
.
Figure 23 shows the signals on the nodes of both FIFOs after the application of a SO
B
pulse, when both FIFOs are initially
full. After a bubble-up delay a DIR
B
pulse is generated, which acts as a SO
A
pulse for FIFO
A
. One word is transferred
from the output of FIFO
A
to the input of FIFO
B
. The requirements of the SO
A
pulse for FIFO
A
is satisfied by the pulse
width of DOR
B
. After a second bubble-up delay an empty space arrives at D
nA
, at which time DIR
A
goes HIGH.
Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
Fig.20 Expanded FIFO for increased word length.
handbook, full pagewidth
MGA685
DIR
OE
SI
DOR
SO
MR
Dn
Qn
5
7404
DIR
OE
SI
DOR
SO
MR
7404
Dn
Qn
SI
MR
OE
SO
composite
DOR
composite
DIR
5
5
5
D
Q
CP
R
74
Q
D
Q
CP
Q
D
Q
CP
74
Q
D
Q
CP
Q
R
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