- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360436 > 74F50729 (NXP Semiconductors N.V.) Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics PDF資料下載
參數(shù)資料
| 型號： | 74F50729 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| 中文描述： | 同步雙D型觸發(fā)器具有邊觸發(fā)器觸發(fā)并以穩(wěn)免疫特色復位 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 94K |
| 代理商： | 74F50729 |
Philips Semiconductors
Product specification
74F50729
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
1990 Sep 14
8
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF,
R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500
MIN
T
amb
= –40
°
C to +85
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
Dn to CPn
Waveform 1
1.5
1.5
2.0
2.0
2.0
2.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Dn to CPn
Waveform 1
1.0
1.0
1.5
1.5
1.5
1.5
ns
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
CPn pulse width,
high or low
Waveform 2
3.0
4.0
3.5
6.0
3.5
6.0
ns
SDn, RDn pulse width, low
Waveform 3
3.5
4.0
4.0
ns
Recovery time
SDn, RDn to CPn
Waveform 3
6.0
6.5
6.5
ns
t
rec
Recovery time
SDn to RDn or RDn to SDn
Waveform 3
6.0
1.0
1.0
ns
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
M
V
M
CPn
V
M
V
M
V
M
V
M
V
M
V
M
t
su
(H)
t
h
(H)
Dn
Qn
V
M
t
w
(H)
1/f
max
t
su
(L)
t
h
(L)
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SF00049
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and
maximum clock frequency
SDn or RDn
V
M
V
M
t
rec
CPn
SF00603
Waveform 3. Recovery time for set or reset to output
V
M
V
M
RDn
V
M
Qn
V
M
V
M
V
M
t
PLH
Qn
t
w
(L)
t
PHL
t
PHL
t
PLH
SDn
V
M
V
M
t
w
(L)
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, Qn
V
M
V
M
t
sk(o)
Qn, Qn
SF00590
Waveform 4. Output skew
相關PDF資料 |
PDF描述 |
|---|---|
| 74F5074 | Synchronizing dual D-type flip-flop/clock driver(同步雙D觸發(fā)器/時鐘驅動器) |
| 74F51SCX | 2/2-input and 3/3-input AND-NOR Gate |
| 74F51SJX | 2/2-input and 3/3-input AND-NOR Gate |
| 74F51 | Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate(雙2位寬，2輸入，2方式 ，3輸入與或非門) |
| 74F521DC | Identity Comparator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74F5074 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop/clock driver |
| 74F5074D | 制造商:SGS 功能描述:74F5074 SGS S1I2B 制造商:NXP Semiconductors 功能描述: |
| 74F5074N | 制造商:NXP Semiconductors 功能描述: |
| 74F51 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate |
| 74F51 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。