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參數(shù)資料
| 型號： | 74F50729 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| 中文描述： | 同步雙D型觸發(fā)器具有邊觸發(fā)器觸發(fā)并以穩(wěn)免疫特色復(fù)位 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 94K |
| 代理商： | 74F50729 |
Philips Semiconductors
Product specification
74F50729
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
1990 Sep 14
5
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
7
8
9
10
10
12
10
11
10
10
10
9
10
8
10
7
10
6
10
14
10
15
= f
C
f
I
t’ in nanoseconds
MTBF in seconds
one year
10
6
10
8
10
10
10
12
one week
10,000 years
100 years
SF00589
NOTE:
V
CC
= 5V, T
amb
= 25
°
C,
τ
=135ps, To = 9.8 X 10
6
sec
Figure 4.
TYPICAL VALUES FOR
τ
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
T
amb
= 0
°
C
V
CC
τ
T
0
5.5V
125ps
1.0 X 10
9
sec
1.3 X 10
10
sec
3.4 X 10
13
sec
T
amb
= 25
°
C
T
amb
= 70
°
C
τ
T
0
τ
T
0
138ps
5.4 X 10
6
sec
9.8 X 10
6
sec
5.1 X 10
8
sec
160ps
1.7 X 10
5
sec
3.9 X 10
4
sec
7.3 X 10
4
sec
5.0V
115ps
135ps
167ps
4.5V
115ps
132ps
175ps
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
D
Q
Q
MODE
↑
↑
↑
↑
↑
↑
X
X
H
L
Asynchronous set
X
X
L
H
Asynchronous reset
↑
h
H
L
Load ”1”
↑
↑
↑
↑
↑
↑
l
L
H
Load ”0”
X
NC
NC
Hold
NOTES:
1. H =
2. h
transition
3. L
4. l
transition
5. NC=
6. X =
7.
↑
=
8.
↑
=
High–voltage level
High–voltage level one setup time prior to low–to–high clock
=
=
=
Low–voltage level
Low–voltage level one setup time prior to low–to–high clock
No change from the previous setup
Don’t care
Low–to–high clock transition
Not low–to–high clock transition
LOGIC DIAGRAM
V
= Pin 14
GND = Pin 7
4, 10
3, 11
SD
CP
Q
5, 9
SF00614
2, 12
D
1, 13
RD
6, 8
Q
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