參數(shù)資料
型號(hào): 73S1210F-68MR/F/PH
廠商: Maxim Integrated
文件頁數(shù): 100/126頁
文件大?。?/td> 0K
描述: IC SOC SMART CARD READER 68QFN
標(biāo)準(zhǔn)包裝: 2,500
系列: *
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
75
> EGT
< WWT
CHAR 1
CHAR 2
CHAR
N+1
CHAR
N+2
CHAR
N+3
BLOCK1
BLOCK2
> BWT
< CWT
RECEPTION
TRANSMISSION
T = 1 Mode
CHAR 1
CHAR 2
CHAR N
RST
TSTO(7:0)
ATRTO(15:0)
VCC_OK
RLen(7:0)
CHAR 1
CHAR 2
CHAR N
ATR Timing Parameters
IWT(15:0)
BGT(4:0)
TX
T = 0 Mode
IO
EGT
(By seting Last_TXByte and
TX/RXB=0 during CHAR N,
RX mode will start after last
TX byte)
WWT is set by the value in the BWT registers.
Figure 19: Guard, Block, Wait and ATR Time Definitions
1.7.15.4
Bypass Mode
It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart
cards. This is called Bypass mode. In this mode the embedded firmware will communicate directly with
the selected smart card and drive I/O during transmit and read I/O during receive in order to communicate
with the smart card. In this mode, ATR processing is under firmware control. The firmware must
sequence the interface signals as required. Firmware must perform TS processing, parity checking,
break generation and CRC/LRC calculation (if required).
1.7.15.5
Synchronous Operation Mode
The 73S1210F supports synchronous operation. When sync mode is selected for either interface, the
CLK signal is generated by the ETU counter. The values in c, SCCLK, and SCECLK must be set to
obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the
interface must be selected to obtain a smart card clock signal. In sync mode, input data is sampled on
the rise of CLK, and output data is changed on the fall of CLK.
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