參數(shù)資料
型號： 71V25761SA200BG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 36 CACHE SRAM, 3.1 ns, PBGA119
封裝： BGA-119
文件頁數(shù)： 4/22頁
文件大?。?/td> 627K
代理商： 71V25761SA200BG
6.42
12
IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the
LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
200MHz(5)
183MHz
166MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
5
____
5.5
____
6
____
ns
tCH(1)
Clock High Pulse Width
2
____
2.2
____
2.4
____
ns
tCL(1)
Clock Low Pulse Width
2
____
2.2
____
2.4
____
ns
Output Parameters
tCD
Clock High to Valid Data
____
3.1
____
3.3
____
3.5
ns
tCDC
Clock High to Data Change
1.0
____
1.0
____
1.0
____
ns
tCLZ(2)
Clock High to Output Active
0
____
0
____
0
____
ns
tCHZ(2)
Clock High to Data High-Z
1.5
3.1
1.5
3.3
1.5
3.5
ns
tOE
Output Enable Access Time
____
3.1
____
3.3
____
3.5
ns
tOLZ(2)
Output Enable Low to Output Active
0
____
0
____
0
____
ns
tOHZ(2)
Output Enable High to Output High-Z
____
3.1
____
3.3
____
3.5
ns
Set Up Times
tSA
Address Setup Time
1.2
____
1.5
____
1.5
____
ns
tSS
Address Status Setup Time
1.2
____
1.5
____
1.5
____
ns
tSD
Data In Setup Time
1.2
____
1.5
____
1.5
____
ns
tSW
Write Setup Time
1.2
____
1.5
____
1.5
____
ns
tSAV
Address Advance Setup Time
1.2
____
1.5
____
1.5
____
ns
tSC
Chip Enable/Select Setup Time
1.2
____
1.5
____
1.5
____
ns
Hold Times
tHA
Address Hold Time
0.4
____
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.4
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.4
____
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.4
____
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.4
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.4
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
100
____
ns
tCFG(4)
Configuration Set-up Time
20
____
22
____
24
____
ns
4876 tbl 16
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