48SD6404
M
em
o
ry
4
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
Standby Current in Power Down
( input signal stable)5
I
CC2PS
CKE = V
IL
t
CK = 0
1, 2, 3
2
mA
Standby Current in non power down6
I
CC2N
CKE, CS = V
IH
t
CK = 12 ns
1, 2, 3
20
mA
Standby Current in non power down
( Input signal stable)7
I
CC2NS
CKE = V
IH
t
CK = 0
1, 2, 3
9
mA
Active standby current in
power down1, 2, 4
I
CC3P
CKE = V
IL
t
CK = 12 ns
1, 2, 3
4
mA
Active standby current in power down
(input signal stable)2,5
I
CC3PS
CKE = V
IL
t
CK = 0
1, 2, 3
3
mA
Active standby power in
non power down1, 2, 6
I
CC3N
CKE, CS = V
IH
t
CK = 12 ns
1, 2, 3
30
mA
Active standby current in non power
down ( input signal stable)2,7
I
CC3NS
CKE = V
IH
t
CK = 0
1, 2, 3
15
mA
Burst Operating Current11, 2,8
CAS Latency = 2
CAS Latency = 3
I
CC4
t
CK = min
BL = 4
1, 2, 3
110
145
mA
Refresh Current3
I
CC5
t
RC = min
1, 2, 3
220
mA
Self Refresh current9
I
CC6
V
IH>VCC - 0.2V
V
IL < 0.2 V
1, 2, 3
3
mA
Input Leakage Current
I
LI
0<V
IN<VCC
1, 2, 3
-1
1
uA
Output Leakage Current
I
LO
0<VOUT<V
CC
1, 2, 3
-1.5
1.5
uA
Output high voltage
V
OH
I
OH = -4mA
1, 2, 3
2.4
V
Output low voltage
V
OL
I
OL = 4 mA
1, 2, 3
0.4
V
1. I
CC1 depends on output load conditions when the device is selected. ICC1 (max) is specified with the output open.
2. One bank operation.
3. Input signals are changed once per one clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals are V
IH or VIL fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current. Self refresh should only be used at temperatures below 70°C.
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(V
CC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125° C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST CONDITIONS
SUBGROUPS
MIN
MAX
UNITS