參數(shù)資料
型號(hào): 48SD6404
廠商: Maxwell Technologies, Inc
英文描述: CAP 2.2UF 50V CERAMIC MONO 20%
中文描述: 256 MB的SDRAM的16梅格× 4位× 4,銀行
文件頁(yè)數(shù): 26/42頁(yè)
文件大?。?/td> 596K
代理商: 48SD6404
48SD6404
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32
All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer than becomes
High-Z after the clock defined by I
HZP , there is a case of interruption to burst read data. Output will be
interrupted if the precharge command is input during burst read. To read all data by burst read, the clocks
defined by I
EP must be assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE command Interval (same bank: To output all data)
CAS Latency = 2, Burst Length = 4
CAS Latency = 3, Burst Length = 4
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