參數(shù)資料
型號: 48SD6404
廠商: Maxwell Technologies, Inc
英文描述: CAP 2.2UF 50V CERAMIC MONO 20%
中文描述: 256 MB的SDRAM的16梅格× 4位× 4,銀行
文件頁數(shù): 20/42頁
文件大?。?/td> 596K
代理商: 48SD6404
48SD6404
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All data sheets are subject to change without notice
2005 Maxwell Technologies
All rights reserved.
256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM
01.11.05 Rev 2
Read command to Write command Interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQM must be set High so the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 cycle, provided that the other bank is in the bank-active state. However, DQM must be set High
so that the output buffer becomes High-Z before data input.
相關PDF資料
PDF描述
48TQFP 48 PIN TQFP/TQN PACKAGE OUTLINE
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49502-0200 1.25 W/B Conn. Housing(New)
49502-0500 1.25 W/B Conn. Housing(New)
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