參數(shù)資料
型號(hào): 440GP
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440GP Embedded Processor
中文描述: 440GP的Power PC嵌入式處理器
文件頁數(shù): 59/83頁
文件大?。?/td> 773K
代理商: 440GP
440GP – Power PC 440GP Embedded Processor
62
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
Notes
PCIXClk input frequency (asynchronous mode)
133.33
MHz
2
PCIXClk period (asynchronous mode)
7.5
ns
PCIXClk input high time
40% of nominal period
60% of nominal period
ns
PCIXClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
2.5
MHz
EMCMDClk period
400
ns
EMCMDClk output high time
160
ns
EMCMDClk output low time
160
ns
EMCTxClk input frequency MII(RMII)
2.5(5)
25(50)
MHz
EMCTxClk period MII(RMII)
40(20)
400(200)
ns
EMCTxClk input high time
35% of nominal period
ns
EMCTxClk input low time
35% of nominal period
ns
EMCRxClk input frequency MII(RMII)
2.5(5)
25(50)
MHz
EMCRxClk period MII(RMII)
40(20)
400(200)
ns
EMCRxClk input high time
35% of nominal period
ns
EMCRxClk input low time
35% of nominal period
ns
EMCRefClk input frequency
50
MHz
EMCRefClk period
20
ns
EMCRefClk input high time
45% of nominal period
55% of nominal period
ns
EMCRefClk input low time
45% of nominal period
55% of nominal period
ns
PerClk output frequency (for ext. master or sync. slaves)
66.66
MHz
PerClk period
15
ns
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
UARTSerClk input frequency
1000/(2TOPB
1+2ns)
MHz
1
UARTSerClk period
2TOPB+2
–ns
1
UARTSerClk input high time
TOPB+1
–ns
1
UARTSerClk input low time
TOPB+1
–ns
1
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