參數(shù)資料
型號: 440GP
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440GP Embedded Processor
中文描述: 440GP的Power PC嵌入式處理器
文件頁數(shù): 56/83頁
文件大?。?/td> 773K
代理商: 440GP
440GP – Power PC 440GP Embedded Processor
6
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
PPC440GP Functional Block Diagram
The PPC440GP is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus Architecture.
Note: IBM CoreConnect buses provide:
128-bit PLB interfaces up to 133.33MHz
32-bit OPB interfaces up to 66.66MHz, 266MB/s
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
Processor Core
DCR Bus
32KB
On-chip Peripheral Bus (OPB)
GPIO
IIC
UART
DMA
Bridge
Processor Local Bus (PLB)
DDR SDRAM
External
Bus
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
Controller
OPB
Interrupt
Controller
Arb
32-bit addr
32-bit data
13-bit addr
32/64-bit data
External
Bus Master
Controller
Universal
I-Cache
32KB
D-Cache
(4-Channel)
133MHz max
66MHz max
SRAM
8KB
PPC440
45 internal
13 external
PCI-X
Bridge
x2
MAL
Ethernet
x2
133MHz max
DCRs
1 MII
or
2 RMII
GP
Timers
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