參數(shù)資料
型號(hào)： 440GP
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GP Embedded Processor
中文描述： 440GP的Power PC嵌入式處理器
文件頁(yè)數(shù)： 44/83頁(yè)
文件大?。?/td> 773K
代理商： 440GP
440GP – Power PC 440GP Embedded Processor
AMCC
49
Revision 1.07 – October 4, 2007
Data Sheet
DDR SDRAM Interface
BA0:1
Bank Address supporting up to four internal banks.
O
2.5V SSTL_2
BankSel0:3
Selects up to four external DDR SDRAM banks.
O
2.5V SSTL_2
CAS
Column Address Strobe.
O
2.5V SSTL_2
ClkEn0:3
Clock Enable. One for each bank.
O
2.5V SSTL_2
DM0:8
Memory write data byte lane masks. MEMDM8 is the byte lane
mask for the ECC byte lane.
O
2.5V SSTL_2
DQS0:8
Byte lane data strobe. DQS8 is the data strobe for the ECC byte
lane.
I/O
2.5V SSTL_2
ECC0:7
ECC check bits 0:7.
I/O
2.5V SSTL_2
MemAddr00:12
Memory address bus.
O
2.5V SSTL_2
MemClkOut0
Subsystem clock.
O
2.5V SSTL_2
MemData00:63
Memory data bus.
I/O
2.5V SSTL_2
MemVRef1:2
Memory reference voltage (SVREF) input.
I
Voltage Ref
Receiver
RAS
Row Address Strobe.
O
2.5V SSTL_2
WE
Write Enable.
O
2.5V SSTL_2
Ethernet Interface
EMCCD,
EMC1RxErr
MII: Collision detection
RMII 1: Receive error
I/O
5V tolerant
3.3V LVTTL
EMCCrS,
EMC0CrSDV
MII: Carrier sense
RMII 0: Carrier sense data valid
I/O
5V tolerant
3.3V LVTTL
EMCMDClk
MII and RMII: Management data clock
O
5V tolerant
3.3V LVTTL
EMCMDIO
MII and RMII: Transfer command and status information between
MII and PHY
I/O
5V tolerant
3.3V LVTTL
EMCRxD0:3,
EMC0RxD0:1,
EMC1RxD0:1
MII: Receive data
RMII 0: Receive data
RMII 1: Receive data
I/O
5V tolerant
3.3V LVTTL
EMCRxDV,
EMC1CrSDV
MII: Receive data valid
RMII 1: Carrier sense data valid
I
5V tolerant
3.3V LVTTL
EMCRxClk
MII: Receive clock
I
5V tolerant
3.3V LVTTL
EMCRxErr,
EMC0RxErr
MII: Receive error
RMII 0: Receive error
I
5V tolerant
3.3V LVTTL
EMCTxClk,
EMCRefClk
MII: Transmit clock
RMII: Reference clock
I
5V tolerant
3.3V LVTTL
5
EMCTxD0:3,
EMC0TxD0:1,
EMC1TxD0:1
MII: Transmit data
RMII 0: Transmit data
RMII 1: Transmit data
O
5V tolerant
3.3V LVTTL
Signal Functional Description (Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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參數(shù)描述
440GR 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 440GR Embedded Processor
440GRX 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440GRx Embedded Processor
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