FAST BOOT BLOCK DATASHEET
E
32
PRODUCT PREVIEW
8.5
AC Characteristics
—Read-Only Operations
(1,6)
—
Extended Temperature
Product
–95
–120
V
CC
Notes
3.0 V–3.6 V 2.7 V–3.6 V
2.7 V–3.6 V
#
Sym
Parameter
Min
Max
Min
Max
Min
Max Unit
R1
t
CLK
CLK Period
15
15
15
ns
R2
t
CH
(t
CL
)
CLK High (Low) Time
2.5
2.5
2.5
ns
R3
t
CHCL
CLK Fall (Rise) Time
5
5
5
ns
R4
t
AVCH
Address Valid Setup to CLK
7
7
7
ns
R5
t
VLCH
ADV# Low Setup to CLK
7
7
7
ns
R6
t
ELCH
CE# Low Setup to CLK
7
7
7
ns
R7
t
CHQV
CLK to Output Delay
14
16
23
ns
R8
t
CHQX
Output Hold from CLK
5
5
5
ns
R9
t
CHAX
Address Hold from CLK
3
10
10
10
ns
R10
t
CHTL
CLK to WAIT# delay
5
13
16
23
ns
R11
t
AVVH
Address Setup to ADV# High
10
10
10
ns
R12
t
ELVH
CE# Low to ADV# High
10
10
10
ns
R13
t
AVQV
Address to Output Delay
90
95
120
ns
R14
t
ELQV
CE# Low to Output Delay
2
90
95
120
ns
R15
t
VLQV
ADV# Low to Output Delay
90
95
120
ns
R16
t
VLVH
ADV# Pulse Width Low
10
10
10
ns
R17
t
VHVL
ADV# Pulse Width High
4
10
10
10
ns
R18
t
VHAX
Address Hold from ADV# High
3
3
3
3
ns
R19
t
APA
Page Address Access Time
21
23
30
ns
R20
t
GLQV
OE# Low to Output Delay
25
25
30
ns
R21
t
RHQV
RST# High to Output Delay
600
600
600
ns
R22
t
EHQZ
t
GHQZ
CE# or OE# High to Output in
High Z, Whichever Occurs First
4
25
25
25
ns
R23
t
OH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
4
0
0
0
ns
NOTES:
1.
2.
3.
4.
5.
6.
See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
OE# may be delayed up to t
ELQV
–t
GLQV
after the falling edge of CE# without impact on t
ELQV
.
Address hold in synchronous burst-mode is defined as t
CHAX
or t
VHAX
, whichever timing specification is satisfied first.
Sampled, not 100% tested.
Output loading on WAIT# equals 15 pF.
Data bus voltage must be less than or equal to V
CCQ
when a read operation is initiated to guarantee AC specifications.