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參數(shù)資料
| 型號： | 28F160F3 |
| 英文描述： | 5V/3.3V or Adjustable, Low-Dropout, Low-IQ, 500mA Linear Regulators |
| 中文描述： | 快速啟動塊閃存的8和16兆比特 |
| 文件頁數(shù)： | 13/47頁 |
| 文件大小： | 277K |
| 代理商： | 28F160F3 |
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E
3.1.5
FAST BOOT BLOCK DATASHEET
13
PRODUCT PREVIEW
RESET
The device enters a reset mode when RST# is
driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance
state.
After return from reset, a time t
PHQV
is required until
outputs are valid, and a delay (t
PHWL
or t
PHEL
) is
required before a write sequence can be initiated.
After this wake-up interval, normal operation is
restored. The device defaults to read array mode,
the status register is set to 80H, and the read
configuration register defaults to asynchronous
page-mode reads.
If RP# is taken low during a block erase or program
operation, the operation will be aborted and the
memory contents at the aborted location are no
longer valid. See Figure 21 for detailed information
regarding reset timings.
4.0
COMMAND DEFINITIONS
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Table 2. Bus Operations
Mode
Notes
RST#
CE#
ADV#
OE#
WE#
Address
V
PP
DQ
0
–15
Reset
V
IL
V
IH
V
IH
V
IH
V
IH
X
X
X
X
X
X
High Z
Standby
V
IH
V
IL
V
IL
V
IL
X
X
X
X
X
High Z
Output Disable
X
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
X
X
High Z
Read
1,2
V
IL
V
IL
X
X
D
OUT
See
Table 4
Read Identifier
Codes
See
Table 4
X
Write
3,4
V
IH
V
IL
V
IL
V
IH
V
IL
X
X
D
IN
NOTES:
1.
2.
Refer to DC Characteristics When V
PP
≤
V
PPLK
, memory contents can be read, but not altered.
X can be V
or V
IH
for control and address input pins and V
PPLK
or V
PPH1/2
for V
PP
. See DC Characteristicsfor V
PPLK
and
V
PPH1/2
voltages.
Command writes involving block erase or program are reliably executed when V
PP
= V
PPH1/2
and V
CC
= V
CC1/2
(see Section 8 for operating conditions at different temperatures).
Refer to Table 3 for valid D
IN
during a write operation.
3.
4.
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