FAST BOOT BLOCK DATASHEET
E
26
PRODUCT PREVIEW
5.0
DATA PROTECTION
The Fast Boot Block flash memory architecture
features hardware-lockable main blocks and two
parameter blocks, so critical code can be kept
secure
while
other
programmed or erased as necessary.
parameter
blocks
are
5.1
V
PP
≤
V
PPLK
for Complete
Protection
The V
PP
programming voltage can be held low for
complete write protection of all blocks in the flash
device. When V
PP
is below V
PPLK
, any block erase
or program operation will result in a error, prompting
the corresponding status register bit (SR.3) to be
set.
5.2
WP# = V
IL
for Block Locking
The lockable blocks are locked when WP# = V
IL
;
any block erase or program operation to a locked
block will result in an error, which will be reflected in
the status register. For top configuration, the top
two parameter and all main blocks (blocks #37,
#38, and #0 through 30 for the 16-Mbit, blocks #21,
#22, and #0 through #14 for the 8-Mbit) are
lockable. For the bottom configuration, the bottom
two parameter and all main blocks (blocks #0, #1,
and #8 through #38 for the 16-Mbit, blocks #0, #1,
and #8 through #22 for the 8-Mbit) are lockable.
Unlocked blocks can be programmed or erased
normally (unless V
PP
is below V
PPLK
).
5.3
WP# = V
IH
for Block Unlocking
WP# controls all block locking and V
PP
provides
protection against spurious writes. Table 9 defines
the write protection methods.
Table 9. Write Protection Truth Table
V
PP
WP#
RST#
Write Protection
Provided
X
X
V
IL
All Blocks Locked
V
IL
X
V
IH
All Blocks Locked
≥
V
PPLK
V
IL
V
IH
Lockable
Blocks Locked
≥
V
PPLK
V
IH
V
IH
All
Blocks Unlocked
6.0
V
PP
VOLTAGES
Intel’s Fast Boot Block flash memory family
provides in-system programming and erase at
2.7 V–3.6 V
(3.0 V–3.6 V
temperature) V
PP
. For customers requiring fast
programming in their manufacturing environment,
this family of products includes an additional low-
cost, high-performance 12 V programming feature.
for
automotive
The 12 V V
PP
mode enhances programming
performance during short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12 V may be applied
to V
PP
during block erase and program operations
for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. V
PP
may
be connected to 12 V for a total of 80 hours
maximum. Stressing the device beyond these limits
may cause permanent damage.
7.0
POWER CONSUMPTION
While in operation, the flash device consumes
active power. However, Intel Flash devices have
power savings that can significantly reduce overall
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is idle. If CE# is deasserted, the
flash enters its standby mode, where current
consumption is even lower. The combination of
these features minimizes overall memory power
and system power consumption.
7.1
Active Power
With CE# at a logic-low level and RST# at a logic-
high level, the device is in active mode. Active
power is the largest contributor to overall system
power consumption. Minimizing active current has a
profound effect on system power consumption,
especially for battery-operated devices.
7.2
Automatic Power Savings
Automatic Power Savings (APS) provides low-
power operation during active mode, allowing the
flash to put itself into a low current state when not
being accessed. After data is read from the memory
array, the device’s power consumption enters the
APS mode where typical I
CC
current is comparable
to I
CCS
. The flash stays in this static state with
outputs valid until a new location is read.