15. AC TIMING SPECIFICAT" />
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鍨嬭櫉(h脿o)锛� 20-668-0003
寤犲晢锛� Rabbit Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 65/228闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CPU RABBIT2000 30MHZ 100PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 66
绯诲垪锛� Rabbit 2000
铏曠悊鍣ㄩ鍨嬶細 Rabbit 2000 8-浣�
閫熷害锛� 30MHz
闆诲锛� 2.7V锛�3V锛�3.3V锛�5V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 100-BQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-PQFP锛�14x20锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 20-668-0003-ND
316-1062
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151
15. AC TIMING SPECIFICATIONS
The Rabbit 2000 processor may be operated at voltages between 2.5 V and 5.5 V, and at
temperatures from 鈥�40掳C to +85掳C with use possible use over the range -55掳C to +120掳C.
Most users will operate the Rabbit at either 5.0 V or 3.3 V. The most computation per watt
is obtained at approximately 3.3 V. The highest practical speed is usually obtained at 5 V.
The Rabbit is available in one version, which has a maximum clock speed of 29.4 MHz over the
industrial temperature range of -40掳C to +85掳C. The R30 has a maximum clock speed of 18.9
MHz at 3.3 V 卤10%. The maximum clock speed is 11.5 MHz at 2.5 V.
If a half-speed crystal is used with the clock doubler to achieve the desired clock speed, the
maximum clock speed must be reduced by 4% to allow for an up to 4% asymmetry (52/48)
in the waveform generated by the oscillator. This is because the clock doubler uses the inter-
mediate edge to generate the double frequency. If the clock doubler is used to double
14.7456 MHz to 29.4912 MHz, the operating temperature should be limited to 70掳C.
To optimize power consumption, the usual strategy is to use a supply voltage between 3 V
and 3.5 V, and the clock speed should be adjusted downward as far as feasible. This will
give the maximum computation per watt.
Table 15-1. Rabbit Basic Worst-Case Timings
2.50 V min.
-40掳C鈥�
+85掳C
3.3 V 卤10%
-40掳C鈥�
+85掳C
3.3V 卤5%
-40掳C鈥�
+70掳C
5.0 V 卤10%
-40掳C鈥�
+85掳C
5.0 V 卤 5%
-40掳C鈥�
+70掳C
Maximum clock speed
11.5 MHz
17.5 MHz
19.25 MHz
29.5 MHz
31.5 MHz
Maximum clock speed
generated using clock
doubler
11.06 MHz
16.75 MHz
18.5 MHz
28.5 MHz
30.0 MHz
Tadr output delay with
20 pF address line load
15 ns
11 ns
10 ns
8 ns
7 ns
Tadr output delay with
70 pF address line load
27 ns
21 ns
19 ns
15 ns
14 ns
Tsetup
4 ns
3 ns
2 ns
Toe delay from clock to
output enable (10 pF load)
12 ns
8 ns
6 ns
5 ns
2001.01.31
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
AMM36DRES CONN EDGECARD 72POS .156 EYELET
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IDT7133LA20G IC SRAM 32KBIT 20NS 68PGA
FMC65DREH-S734 CONN EDGECARD 130POS .100 EYELET
EMC65DTEF CONN EDGECARD 130POS .100 EYELET
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
20-668-0011 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU Rabbit 3000A LQFP Microprocessor RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
20-668-0016 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU Rabbit 3000 TFBGA Microprocessor RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
2066-8001-90 鍒堕€犲晢:TE CONNECTIVITY 鍔熻兘鎻忚堪:RF COAXIAL PANEL MOUNT CONNECTOR
20-668-0022 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU Rabbit 4000 LQFP Microprocessor RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
20-668-0024 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU Rabbit 4000 LQFP Microprocessor RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
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