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參數(shù)資料
| 型號(hào)： | 20-668-0003 |
| 廠商： | Rabbit Semiconductor |
| 文件頁(yè)數(shù)： | 223/228頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CPU RABBIT2000 30MHZ 100PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | Rabbit 2000 |
| 處理器類型： | Rabbit 2000 8-位 |
| 速度： | 30MHz |
| 電壓： | 2.7V，3V，3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
| 包裝： | 托盤(pán) |
| 其它名稱： | 20-668-0003-ND 316-1062 |
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88
Rabbit 2000 Microprocessor User’s Manual
7.10 Bootstrap Operation
The device provides the option of bootstrap from any of three sources: from the Slave
Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous
mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is
disabled if (SMODE1, SMODE0) = (0, 0).
Bootstrap operation inhibits the normal fetch of code from memory, and instead substi-
tutes the output of a small internal boot ROM for program fetches. This bootstrap program
reads groups of three bytes from the selected peripheral device. The first byte is the most
significant byte of a 16-bit address, followed by the least-significant byte of a 16-bit
address, followed by a byte of data. The bootstrap program then writes the byte of data to
the downloaded address and jumps back to the start of the bootstrap program. The most
significant bit of the address is used to determine the destination for the byte of data. If this
bit is zero, the byte is written to the memory location addressed by the downloaded
address. If this bit is one, the byte is written to the internal peripheral addressed by the
downloaded address. Note that all of the memory control signals continue to operate nor-
mally during bootstrap.
Execution of the bootstrap program automatically waits for data to become available from
the selected peripheral, and each byte transferred automatically resets the watchdog timer.
However, the watchdog timer still operates, and bytes must be transferred often enough to
prevent the watchdog timer from timing out.
Bootstrap operation is terminated when the SMODE pins are set to zero. The SMODE
pins are sampled just prior to fetching the first instruction of the bootstrap program. If the
SMODE pins are zero, instructions are fetched from normal memory starting at address
0x0000. The Slave Port Control register allows the bootstrap operation to be terminated
remotely. Writing a one to bit 7 of this register causes the bootstrap operation to terminate
immediately. So the sequence 0x80, 0x24, and 0x80 will terminate bootstrap operation.
Bootstrap operation is not restricted to the time immediately after reset because the boot
ROM is addressed by only the four least significant bits of the address. So any time that
the address ends in four zeros, if the SMODE pins are non-zero and bit 7 of the SPCR is
zero, the bootstrap program will begin execution. This allows in-line downloading from
the selected bootstrap port. Upon completion of the bootstrap operation, either by return-
ing the SMODE pins to zero or setting the bit in the SPCR, execution will continue from
where it was interrupted for the bootstrap operation.
The Slave Port is selected for bootstrap operation when (SMODE1, SMODE0) = (0, 1). In
this case the pins of Parallel Port A are used for a byte-wide data bus, and selected pins of
Parallel Ports B and E are used for the Slave Port control signals. Only Slave Port Data
Register 0 is used for bootstrap operation, and any writes to the other data registers will be
ignored by the processor, and can actually interfere with the bootstrap operation by mask-
ing the Write Empty signal.
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