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參數資料
| 型號： | 1977IFE |
| 廠商： | Linear Technology Corporation |
| 英文描述： | High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100uA Quiescent Current |
| 中文描述： | 高電壓，500kHz降壓1.5安培的電流型開關穩(wěn)壓器的靜態(tài)電流為100uA |
| 文件頁數： | 18/24頁 |
| 文件大?。?/td> | 288K |
| 代理商： | 1977IFE |
LT1977
18
1977f
APPLICATIOU
In addition to the shutdown feature, the LT1977 has an
undervoltage lockout function. When the input voltage is
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low V
IN
to V
OUT
ratios refer to Figure 8 and
the following:
W
U
U
V
R
V
R
( )
3
V
R
I
V
V
V
R
UVLO
SHDN
3
SHDN
2
SHDN
SHDN
HYST
OUT
=
+
+
+
=
1
R1 should be chosen to minimize quiescent current during
normal operation by the following equation:
R
V
)
(
V
I
IN
SHDN MAX
1
2
1 5
.
=
(
)
–
(
)
Example:
R
A
M
R
M
1
M
A
M
k
1
12 2
1 5 5
5 1 3
1 3
.
3
6 5
.
1
1 3
.
6 49
.
408
=
μ
)
=
=
)
=
(Nearest 1% 412k)
μ
=
–
.
.
–
–
(Nearest 1% 6.49M )
R2=
1.3
7–1.3
1.3M
See the Typical Performance Characteristics section for
graphs of SHDN and V
IN
currents versus input voltage.
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between
30%
and
70%
to the LT1977 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to
700kHz
. This means that minimum
practical sync frequency is equal to the worst-case high
Figure 8. Undervoltage Lockout
ENABLE
1.3V
1977 F08
3
μ
A
SHDN
R2
2.4V
–
+
SHDN
COMP
–
+
V
COMP
15
V
IN
V
OUT
LT1977
4
R1
R3
self-oscillating frequency (
575kHz
), not the typical oper-
ating frequency of
500kHz
. Caution should be used when
synchronizing above
575kHz
because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid any
hazardous conditions for the SW pin.
If no synchronization is required this pin should be con-
nected to ground.
POWER GOOD
The LT1977 contains a power good block which consists
of a comparator, delay timer and active low flag that allows
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the delay period. When the voltage on
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