
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 43
PIC16F870/871
4.6
Writing to the FLASH Program
Memory
When the PIC16F870/871 are fully code protected or
not code protected, a word of the FLASH program
memory may be written provided the WRT configura-
tion bit is set. If the PIC16F870/871 are partially code
protected, then a word of FLASH program memory
may be written if the word is in a non-code protected
segment of memory and the WRT configuration bit is
set. To write a FLASH program location, the first two
bytes of the address must be written to the EEADR and
EEADRH registers and two bytes of the data to the
EEDATA and EEDATH registers, set the EEPGD con-
trol bit (EECON1<7>), and then set control bit WR
(EECON1<1>). The sequence in Example 4-4 must be
followed to initiate a write to program memory.
The microcontroller will then halt internal operations
during the next two instruction cycles for the T
PEW
(parameter D133) in which the write takes place. This
is not SLEEP mode, as the clocks and peripherals will
continue to run. Therefore, the two instructions follow-
ing the “
BSF EECON, WR
” should be
NOP
instructions.
After the write cycle, the microcontroller will resume
operation with the 3rd instruction after the EECON1
write instruction.
EXAMPLE 4-4:
FLASH PROGRAM WRITE
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW ADDRH ;
MOVWF EEADRH ; MSByte of Program Address to read
MOVLW ADDRL ;
MOVWF EEADR ; LSByte of Program Address to read
MOVLW DATAH ;
MOVWF EEDATH ; MS Program Memory Value to write
MOVLW DATAL ;
MOVWF EEDATA ; LS Program Memory Value to write
BSF STATUS, RP0 ; Bank 3
BSF EECON1, EEPGD ; Point to PROGRAM memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required
MOVWF EECON2 ; Write 55h
Sequence
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
NOP ; Instructions here are ignored by the microcontroller
NOP
; Microcontroller will halt operation and wait for
; a write complete. After the write
; the microcontroller continues with 3rd instruction
BSF INTCON, GIE ; Enable Interrupts
BCF EECON1, WREN ; Disable writes