參數(shù)資料
型號(hào): 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 測(cè)試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁(yè)數(shù): 46/92頁(yè)
文件大小: 1041K
代理商: 1215E
50
Agere Systems Inc.
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
CBIST: Control-BIST Register
Purpose
Provides facility for selection and execution of BSM2 BIST functions (memory, random logic, memory retention)
provides memory BIST result signature.
Address (Octal)
05
Format
Default (Hex)
CBIST = 0000
Read-only Bits
Bits CBIST[15:07] are read-only.
Passing Signatures
Memory BIST:
MEMSIG[5:0] = 00000 (binary)
Random Logic BIST:
BSR = 000BDB3A (hex)
Description
MEMSKIP
(Memory BIST Skip Bit)—If the value of this bit is 1, the memory BIST operation will be skipped when
the XECBIST bit (below) is set and BIST is executed. If the value of this bit is 0, then memory BIST
will be activated when BIST is executed.
RLSKIP
(Random Logic BIST Skip Bit)—If the value of this bit is 1, the random logic BIST operation will be
skipped when the XECBIST bit (below) is set and BIST is executed. If the value of this bit is 0, then
random logic BIST will be activated when BIST is executed.
MEMRETE (Memory BIST Retention Test Enable Bit)—If the value of this bit is 1, the memory BIST retention test
will occur. Otherwise, the retention test is skipped. Retention testing is normally done only during
manufacture. This test checks for leakage paths that check the volatility of the memory. In order to
carry out this test in the field, the master clock (TCKIN) must be stopped at particular intervals into the
memory test. Contact Agere for further details regarding implementation of this test.
15—10
09
08
07
MEMSIG[5:0] RL_DONE MEMDONE SYSDONE
06-05
04
03
02
01
00
unused
BIST_IE XECBIST MEMRETE RLSKIP MEMSKIP
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