參數(shù)資料
型號: 1215E
英文描述: TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述: 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁數(shù): 16/92頁
文件大?。?/td> 1041K
代理商: 1215E
Agere Systems Inc.
23
User Manual
April 2001
497AE and 1215E Boundary-Scan Master 2
Advanced Operational Mode
BIST—Self-Test of the BSM2 (continued)
Programming BIST in the BSM2
Initiating and Terminating BIST
In the BSM2, BIST is initiated by writing a 1 to the
XECBIST bit in the CBIST register.
Writing a 0 to the XECBIST bit not only terminates a
BIST operation, but also clears the DONE bits and ini-
tializes miscellaneous internal BIST control registers.
Execution of BIST may be shut off at any time by writ-
ing a 0 to the XECBIST bit. After normal BIST termina-
tion, the XECBIST bit also should be set to 0.
Parameters Controlling BIST Execution
The parameters for running BSM2 self-test are pro-
grammed using the MEMSKIP, RLSKIP, and
MEMRETE bits of the CBIST register.
If the value of the MEMSKIP bit is 1, the memory BIST
operation will be skipped when BIST is executed. If the
value of this bit is 0, then memory BIST will be acti-
vated when BIST is executed.
Similarly, if the value of the RLSKIP bit is 1, the random
logic BIST operation will be skipped when BIST is exe-
cuted. If the value of this bit is 0, then random logic
BIST will be activated when BIST is executed.
If the value of the MEMRETE bit is 1, the memory BIST
retention test will be included in the BIST execution.
Otherwise, the retention test is skipped. Retention test-
ing is normally done only during manufacture. This test
checks for leakage paths that check the volatility of the
memory. In order to carry out this test in the field, the
master clock (TCKIN) must be stopped at particular
intervals into the memory test. Contact Agere for fur-
ther details regarding implementation of this test.
A pseudocode example of programming, executing,
and terminating BSM2 BIST is included in Appendix A
under the heading Programming Self-Test of the
BSM2.
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