參數(shù)資料
型號： 1215E
英文描述： TEST/JTAG SUPPORT|CMOS|QFP|48PIN|PLASTIC
中文描述： 測試/ JTAG支持|的CMOS | QFP封裝| 48PIN |塑料
文件頁數(shù)： 42/92頁
文件大?。?/td> 1041K
代理商： 1215E
Agere Systems Inc.
47
User Manual
April 2001
Advanced Operational Mode
497AE and 1215E Boundary-Scan Master 2
Appendix B—BSM2 Register Descriptions (continued)
STAT: Status Register (continued)
TAPS[3:0]
(TAP State Bits)—These four bits encode the current state of the TAP controllers of devices on the
currently selected/attached B-S chain. The STAT register is read-only. The only way these bits will be
altered is by the TAP State Tracker, or by executing the Jump Command or the Reset Command (see
description of the Execution Bits in the CUTI register). In response to the Jump Command (page 12),
the TAPS bits immediately record the destination TAP Controller state. The encoding used is as fol-
lows:
USRN
(USERIN Signal Value Bit)—This bit contains the current value from the USERIN pin. The value of the
signal on USERIN is not latched by the BSM2. Stability of this signal (as required) is the responsibility
of the user. This bit is only functional in the 1215E. In the 497AE, this bit always has the value 1.
IDL0
(Idle Counter State Bit)—When the value of this bit is 0, the IDLE counter register has not yet counted
down to zero. When the IDLE counter register has counted down to zero, this bit has the value 1.
(See description of the IDT[1:0] bits, above.)
TVX0
(TVX Counter State Bit)—When the value of this bit is 0, the TVX counter register has not yet counted
down to zero. When the TVX counter has counted down to zero, this bit has the value 1.
DONE
(Scan Done Bit)—The value of this bit is 1 if and only if the most recently initiated scan process has
terminated. Otherwise, the value of this bit is 0. The conditions under which the value of the bit will be
1 are as follows:
If the last scan operation was in normal (non-ATPG) mode, then the TVX and IDLE counter registers
are at zero.
If the last scan operation was via ATPG and the ATPG mode is 011, then the SDC and LPC registers
are at zero.
If the last scan operation was via ATPG and the ATPG mode is
not 011, then the LPC register is at
zero.
In all three cases, the TAP state bits (above) will indicate that the destination TAP Controller state has
been entered.
TAPS[3:0] Value Current TAP Controller State
0000
Test-Logic-Reset
0001
Select-DR-Scan
0010
Capture-DR
0011
Shift-DR
0100
Exit1-DR
0101
Pause-DR
0110
Exit2-DR
0111
Update-DR
1000
Run-Test/Idle
1001
Select-IR-Scan
1010
Capture-IR
1011
Shift-IR
1100
Exit1-IR
1101
Pause-IR
1110
Exit2-IR
1111
Update-IR
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