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CHAPTER 19 STANDBY FUNCTION
323
19.2 Operation of Standby Function
19.2.1 HALT mode
(1)
HALT mode
HALT mode is set by executing the HALT instruction.
The operation status in HALT mode is shown in the following table.
Table 19-1. Operation Statuses in HALT Mode
HALT Mode Operation Status while the Main
System Clock is Running
HALT Mode Operation Status while the Subsystem
Clock is Running
Item
While the Subsystem
Clock is Running
While the Subsystem
Clock is Not Running
While the Main System
Clock is Running
While the Main System
Clock is Not Running
Clock generation
circuit
Can operate with the main system clock
Does not run
CPU
Operation disabled
Port (output latch)
Remains in the state existing before the selection of HALT mode
16-bit timer counter
(TM90)
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Note 2
8-bit timer/event
counter (TM80)
Operation enabled
Operation enabled
Note 3
8-bit timer/event
counter (TM81)
Operation enabled
Operation enabled
Note 4
8-bit timer counter
(TM82)
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Note 2
Watch timer
Operation enabled
Operation enabled
Note 1
Operation enabled
Operation enabled
Note 2
Watchdog timer
Operation enabled
Operation disabled
Serial interface
Operation enabled
Operation enabled
Note 5
SMB
Operation enabled
Operation enabled
Note 6
A/D converter
Operation disabled
Multiplier
Operation disabled
EEPROM
Operation enabled
Operation enabled
Notes 1, 7
Operation enabled
Operation enabled
Notes 2, 7
Low-voltage
indicator
Operation enabled
Note 8
External interrupt
Operation enabled
Note 8
Notes 1.
Operation is enabled while the main system clock is selected.
2.
Operation is enabled while the subsystem clock is selected.
3.
Operation is enabled only when TI80 is selected as the count clock.
4.
Operation is enabled only when TI81 is selected as the count clock.
5.
Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used.
6.
While in slave mode, an interrupt can be generated when an address match is found.
7.
Operation is enabled only when TM80 output is selected (only when TI80 is selected for TM80) as the
count clock.
8.
Maskable interrupt that is not masked