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CHAPTER 7 CLOCK GENERATION CIRCUIT (
μ
PD789197Y Subseries )
114
7.5 Clock Generation Circuit Operation
The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as
standby mode:
Main system clock f
X
Subsystem clock f
XT
CPU clock f
CPU
Clock to peripheral hardware
The operation of the clock generation circuit is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows:
(a)
The slow mode 2 f
CPU
(1.6
μ
s: at 5.0-MHz operation) of the main system clock is selected when the
RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of
the main system clock is stopped .
(b)
Three types of CPU clocks f
CPU
(0.2
μ
s and 0.8
μ
s: main system clock (at 5.0-MHz operation), 61
μ
s:
subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS settings.
(c)
Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the built-in feedback resistor
cannot be used reduces current drain during STOP mode. In a system where a subsystem clock is
used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d)
CSS bit 4 (CSS0) can be used to select the subsystem clock so that low power dissipation operation is
used (at 122
μ
s, 32.768 kHz operation).
(e)
With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
according to bit 7 (MCC) of PCC. HALT mode can be used, but STOP mode cannot.
(f)
The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock. The subsystem clock pulse is supplied to EEPROM timer, 16-bit timer counter 90, 8-bit timer
counter 82, and the watch timer only. So, also at standby, EEPROM timer, 16-bit timer counter 90, 8-
bit timer counter 82, and clock function can keep running. The other hardware stops when the main
system clock stops, because it runs based on the main system clock (except for external clock
pulses).