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參數(shù)資料
| 型號： | μPD72862 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI Host Controller(IEEE1394 主控制器) |
| 中文描述： | IEEE1394連接OHCI主機(jī)控制器（IEEE1394連接主控制器） |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 194K |
| 代理商： | ΜPD72862 |
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Data Sheet S14265EJ2V0DS00
9
μ
PD72862
(2/2)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
PME
O
79
PCI/Cardbus
5/3.3
PME Output
for power management enable.
Caution
The PME pin is not an N-channel open drain structure pin.
Therefore, when using S3, S4, S5 state in ACPI, a
circuit that can separate between the power supply
and the PME pin externally is needed.
ACPI: Advanced Configuration and Power Interface.
Please refer to ACPI Specification.
CLKRUN
I/O
78
PCI/Cardbus
5/3.3
PCICLK Running
as input, to determine the status of PCLK; as
output, to request starting or speeding up clock.
INTA
O
80
PCI/Cardbus
5/3.3
Interrupt
the PCI interrupt request A.
PERR
I/O
16
PCI/Cardbus
5/3.3
Parity Error
is used for reporting data parity errors during all PCI
transactions, except a Special Cycle. It is an output when AD0-
AD31 and PAR are both inputs. It is an input when AD0-AD31 and
PAR are both outputs.
SERR
O
17
PCI/Cardbus
5/3.3
System Error
is used for reporting address parity errors, data parity
errors during the Special Cycle, or any other system error where the
effect can be catastrophic. When reporting address parity errors, it
is an output.
PRST
I
81
-
5/3.3
Reset
PCI reset
PCLK
I
82
-
5/3.3
PCI Clock
33 MHz system bus clock.
1.2 PCI/Cardbus Select Signals: (2 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
CARD_ON
I
54
-
3.3
PCI/Card Select
(1:Cardbus, 0:PCI bus)
CIS Register ON
CARD_ON
CIS_ON
CIS
PME
CIS_ON
I
45
-
3.3
0
0
1
1
0
X
off
on
on
PME
CSTSCHG
CSTSCHG
#
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