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參數(shù)資料
| 型號(hào)： | μPD72862 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI Host Controller(IEEE1394 主控制器) |
| 中文描述： | IEEE1394連接OHCI主機(jī)控制器（IEEE1394連接主控制器） |
| 文件頁(yè)數(shù)： | 10/36頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | ΜPD72862 |
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Data Sheet S14265EJ2V0DS00
10
μ
PD72862
1.3 PHY/Link Interface Signals: (15 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
D0-D7
I/O
59-62,
64-67
9mA
3.3
PHY/Link Bi-directional Data
(ISO-barrier supported)
CTL0,CTL1
I/O
69, 70
9mA
3.3
PHY/Link Bi-directional Control
(ISO-barrier supported)
LREQ
O
73
9mA
3.3
PHY/Link Request
(ISO-barrier supported)
LINKON
I
77
-
3.3
Link-On Request
(ISO-barrier supported)
LPS
O
74
9mA
3.3
Link Power Status
(ISO-barrier supported)
SCLK
I
72
-
3.3
PHY Clock
49.152 MHz (ISO-barrier supported)
DIRECT
I
68
-
3.3
Auxiliary PHY/Link Signal
is used to determine whether the
interconnection between Link and PHY has isolation (‘low’: ISO-
barrier; ‘high’: no ISO-barrier).
1.4 Serial ROM Interface Signals: (3 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
GROM_SDA
I/O
55
6mA
3.3
Serial EEPROM Data Input / Output
GROM_SCL
O
56
6mA
3.3
Serial EEPROM Clock Output
GROM_EN
I
57
-
3.3
Serial EEPROM Enable
(‘high’: GUID Load enabled; ‘low’: GUID
Load disabled)
1.5 Miscellaneous Signal: (1 pin)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
PIN_EN
I
43
-
5/3.3
Pin Enable Input
(High clamped)
1.6 IC: (3 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
IC(H)
I
44
-
3.3
Internally Connected
(High clamped)
IC(L)
I
46, 47
-
3.3
Internally Connected
(Low clamped)
1.7 NC: (5 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
NC
-
48, 49,
52, 53,
58
-
-
Non- Connection
(Open)
Leave them unconnected.
1.8 V
DD
: (8 pins)
V
DD
(5 V PCI or 3.3 V PCI) for PCI I/Os: 11, 37, 92
V
DD
3 V for digital core & PHY/Link I/Os: 1, 25, 51, 75, 97
1.9 V
SS
: (11 pins)
V
SS
: 6, 19, 26, 31, 38, 50, 63, 71, 76, 85, 100
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