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參數(shù)資料
| 型號： | μPD72862 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI Host Controller(IEEE1394 主控制器) |
| 中文描述： | IEEE1394連接OHCI主機(jī)控制器（IEEE1394連接主控制器） |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 194K |
| 代理商： | ΜPD72862 |
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Data Sheet S14265EJ2V0DS00
16
μ
PD72862
2.1.16 Offset_3C Interrupt Line Register
This register provides the interrupt line routing information specific to the
μ
PD72862, the NEC’s implementation of
the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R/W
Default value of 00H. It specifies which input of the host system interrupt controller the
interrupt pin of the
μ
PD72862 is connected to.
2.1.17 Offset_3D Interrupt Pin Register
This register provides the interrupt line routing information specific to the
μ
PD72862, the NEC’s implementation of
the 1394 OpenHCI specification.
Bits
R/W
Description
7-0
R
Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.
2.1.18 Offset_3E Min_Grant Register
This register specifies how long of a burst period the
μ
PD72862 needs, assuming a clock rate of 33MHz.
Resolution is in units of
μ
s. The value should be loaded into the register from the external serial EEPROM upon
power-up reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
2.1.19 Offset_3F Max Lat Register
This register specifies how often the
μ
PD72862 needs to gain access to the PCI-bus, assuming a clock rate of
33MHz. Resolution is in units of
μ
s. The value should be loaded into the register from the external serial
EEPROM after hardware reset, and access to this register through PCI-bus is prohibited.
Bits
R/W
Description
7-0
R
Default value of 00H. Its value contributes to the desired setting for Latency Timer value.
2.1.20 Offset_40 PCI_OHCI_Control Register
This register specifies the control bits that are IEEE1394 OpenHCI specific. Vendor options are not allowed in this
register. It is reserved for OpenHCI use only.
Bits
R/W
Description
0
R/W
PCI global SWAP
Default value of 0. When this bit is 1, all quadrates read from and written to
the PCI Interface are byte swapped, thus a “PCI Global Swap”. PCI addresses for expansion
ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not
required for motherboard implementations.
31-1
R
Reserved
Constant value of all 0.
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