參數(shù)資料
型號(hào)： μPD72862
廠商： NEC Corp.
英文描述： IEEE1394 OHCI Host Controller(IEEE1394 主控制器)
中文描述： IEEE1394連接OHCI主機(jī)控制器（IEEE1394連接主控制器）
文件頁(yè)數(shù)： 17/36頁(yè)
文件大?。?/td> 194K
代理商： ΜPD72862
Data Sheet S14265EJ2V0DS00
17
μ
PD72862
2.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the
Next_Item_Ptr describes the location of the next item in the
μ
PD72862’s Capability List.
Bits
R/W
Description
7-0
R
Cap_ID
Constant value of 01H. The default value identified the Link List item as being the PCI
Power Management registers, while the ID value is assigned by the PCI SIG.
15-8
R
Next_Item_Ptr
Constant value of 00H. It indicated that there are no more items in the Link
List.
2.1.22 Offset_62 Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of the
μ
PD72862.
Bits
R/W
Description
2-0
R
version
Constant value of 001. The power management registers are implemented as defined
in revision 1.0 of PCI Bus Power Management Interface Specification.
3
R
PME clock
Constant value of 0.
4
R
Auxiliary power source
Constant value of 0. The alternative power source is not supported.
5
R
DIS
Constant value of 0.
8,6
R
Reserved
Constant value of 000.
9
R
D1_support
Constant value of 0. The
μ
PD72862 does not support the D1 Power
Management state.
10
R
D2_support
Constant value of 1. The
μ
PD72862 supports the D2 Power Management state.
15-11
R
PME_support
Constant value of 01100.
2.1.23 Offset_64 Power Management Control/Status Register
This is a 16-bit read-only register that provides control status information of the
μ
PD72862.
Bits
R/W
Description
1,0
R/W
PowerState
Default value is undefined. This field is used both to determine the current power
state of the
μ
PD72862 and to set the
μ
PD72862 into a new power state. As D1 is not
supported in the current implementation of the
μ
PD72862, writing of ‘01’ will be ignored.
00: D0 (DMA contexts: ON, Link Layer: ON)
01: Reserved (D1 state not supported)
10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active, Power can be removed)
7-2
R
Reserved
Constant value of 000000.
8
R/W
PME_En
Default value of 0. This field is used to enable the specific power management
features of the
μ
PD72862.
12-9
R
Data_Select
Constant value of 0000.
14,13
R
Data_Scale
Constant value of 00.
15
R/W
PME_Status
Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ is
ignored.
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