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參數(shù)資料
| 型號： | μPD72862 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI Host Controller(IEEE1394 主控制器) |
| 中文描述： | IEEE1394連接OHCI主機(jī)控制器（IEEE1394連接主控制器） |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 194K |
| 代理商： | ΜPD72862 |
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Data Sheet S14265EJ2V0DS00
23
μ
PD72862
(6) W_GENERAL register (Base address + 0x950 - 0x95C)
31
0
W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C)
Field
Bits
R/W
Default value
Description
W_GENERAL_0 -
W_GENERAL_3
31-0
R/W
Undefined
User define value. The value is loaded into GENERAL_registerA - D in
Configuration register (Offset+70H - 7BH).
(7) W_PHYS register (Base address + 0x960)
31
10
9
8
7
3
2
0
- 0 -
- 0 -
- 1 -
W_aPhyEnhanceEnable
W_programPhyEnable
Field
Bits
R/W
Default value
Description
-
31-10
-
-
Reserved. Write 0 to these bits.
W_programPhyEnable
9
R/W
1
programPhyEnable bit. The bit is loaded into HCControl registers in OHCI
register ((Offset+50H bit 23) and (54H bit 23)).
Please refer to the 1394 Open Host Controller Interface Specification/Release
1.0 [5.7].
1: P1394a enhancement is supported.
0. P1394a enhancement is not supported.
W_aPhyEnhanceEnable
8
R/W
0
aPhyEnhanceEnable bit. The bit is loaded into HCControl registers in OHCI
register ((Offset+50H bit 23) and (54H bit 23)).
7-3
-
-
Reserved. Write 0 to these bits.
-
2-0
-
-
Reserved. Write 1 to these bits.
(8) W_CIS register (Base address + 0x980 - 0x984)
31
0
W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984)
Field
Bits
R/W
Default value
Description
W_CIS_EVEN -
W_CIS_ODD
31-0
R/W
Undefined
CIS Area value. The value is loaded into CIS Area in Configuration register
(Offset+80H - FCH).
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