參數(shù)資料
型號: μPD481850
廠商: NEC Corp.
英文描述: Synchronous Graphics Memory (SGRAM)(8M 同步圖形存儲器)
中文描述: 同步圖形存儲器(SGRAM)(8分同步圖形存儲器)
文件頁數(shù): 25/94頁
文件大?。?/td> 1180K
代理商: ΜPD481850
Preliminary Data Sheet
25
μ
PD481850 for Rev.L
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A9 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
/CAS latency
Wrap type
Burst length
: A9 through A7
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be asserted before at least 2
CLK (t
RSC
) have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The table on page 51
shows the relationship of /CAS latency to the clock period and the speed grade of the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page (256 columns).
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The
μ
PD481850 supports
“Sequential mode” and “Interleave mode”.
The table on the page 27 shows the addressing sequence for each burst length.
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