參數(shù)資料
型號(hào)： μPD45256163
廠商： NEC Corp.
英文描述： 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
中文描述： 256M位同步DRAM（256M同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 28/84頁(yè)
文件大?。?/td> 1052K
代理商： ΜPD45256163
28
μ
PD45256441,45256841,45256163
Preliminary Data Sheet
11. Read/Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the
previous read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
QB1
QB2
QB3
QB4
Hi-Z
Read A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
Read B
QA1
1cycle
T9
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst
will begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
DB1
DB2
DB3
DB4
Hi-Z
Write A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
Write B
DA1
1cycle
相關(guān)PDF資料
PDF描述
μPD45256441 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動(dòng)態(tài)RAM)
μPD4564163 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564441 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
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