參數(shù)資料
型號： μPD45256163
廠商： NEC Corp.
英文描述： 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
中文描述： 256M位同步DRAM（256M同步動態(tài)RAM）的
文件頁數(shù)： 18/84頁
文件大?。?/td> 1052K
代理商： ΜPD45256163
18
μ
PD45256441,45256841,45256163
Preliminary Data Sheet
(3/3)
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Notes
Write recovering
H
x
x
x
x
DESL
Nop
→
Enter row active after t
DPL
L
H
H
H
x
NOP
Nop
→
Enter row active after t
DPL
L
H
H
L
x
BST
Nop
→
Enter row active after t
DPL
L
H
L
H
BA, CA, A10 READ/READA
Start read, Determine AP
8
L
H
L
L
BA, CA, A10 WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
x
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write recovering
H
x
x
x
x
DESL
Nop
→
Enter precharge after t
DPL
with auto precharge
L
H
H
H
x
NOP
Nop
→
Enter precharge after t
DPL
L
H
H
L
x
BST
Nop
→
Enter precharge after t
DPL
L
H
L
H
BA, CA, A10 READ/READA
ILLEGAL
3, 8
L
H
L
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
x
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
x
x
x
x
DESL
Nop
→
Enter idle after t
RC
L
H
H
x
x
NOP/BST
Nop
→
Enter idle after t
RC
L
H
L
x
x
READ/WRIT
ILLEGAL
L
L
H
x
x
ACT/PRE/PALL ILLEGAL
L
L
L
x
x
REF/SELF/MRS ILLEGAL
Mode register
H
x
x
x
x
DESL
Nop
→
Enter idle after t
RSC
accessing
L
H
H
H
x
NOP
Nop
→
Enter idle after t
RSC
L
H
H
L
x
BST
ILLEGAL
L
H
L
x
x
READ/WRIT
ILLEGAL
L
L
x
x
x
ACT/PRE/PALL
/REF/SELF/MR
S
ILLEGAL
Notes 1
All entries assume that CKE was active (High level) during the preceding clock cycle.
2.
If all banks are idle, and CKE is inactive (Low level),
μ
PD45256xxx will enter Power down mode.
All input buffers except CKE will be disabled.
3.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4.
If all banks are idle, and CKE is inactive (Low level),
μ
PD45256xxx will enter Self refresh mode. All
input buffers except CKE will be disabled.
5.
Illegal if t
RCD
is not satisfied.
6.
Illegal if t
RAS
is not satisfied.
7.
Must satisfy burst interrupt condition.
8.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9.
Must mask preceding data which don't satisfy t
DPL
.
10.
Illegal if t
RRD
is not satisfied.
Remark
H = High level, L = Low level, x = High or Low level (Don’ t care), V = Valid Data
相關PDF資料
PDF描述
μPD45256441 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
μPD45256841 256M-Bit Synchronous DRAM(256M 同步 動態(tài)RAM)
μPD4564163 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564441 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
μPD4564841 64M-bit Synchronous DRAM(64M同步動態(tài)RAM)
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