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| 型號： | μPD4265165 |
| 廠商： | NEC Corp. |
| 英文描述： | 64 M-Bit Dynamic Ram(64M 動態(tài)存儲器) |
| 中文描述： | 64 m位動態(tài)隨機(jī)存儲器（6400動態(tài)存儲器） |
| 文件頁數(shù)： | 9/48頁 |
| 文件大小： | 535K |
| 代理商： | ΜPD4265165 |
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μ
PD42S65165, 4265165
9
DC Characteristics (Recommended operating conditions unless otherwise noted)
[
μ
PD42S65165, 4265165]
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
RAS, CAS cycling
t
RAC
= 50 ns
150
mA
1, 2, 3
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 60 ns
130
Standby
current
μ
PD42S65165
I
CC2
RAS, CAS
≥
V
IH (MIN.)
, I
O
= 0 mA
1.0
mA
RAS, CAS
≥
V
CC
– 0.2 V, I
O
= 0 mA
0.2
μ
PD4265165
RAS, CAS
≥
V
IH (MIN.)
, I
O
= 0 mA
1.0
RAS, CAS
≥
V
CC
– 0.2 V, I
O
= 0 mA
0.5
RAS only refresh current
I
CC3
RAS cycling, CAS
≥
V
IH (MIN.)
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 50 ns
150
mA
1, 2, 3 ,4
t
RAC
= 60 ns
130
Operating current
(Hyper page mode (EDO))
I
CC4
RAS
≤
V
IL (MAX.)
, CAS cycling
t
HPC
= t
HPC (MIN.)
, I
O
= 0 mA
t
RAC
= 50 ns
120
mA
1, 2, 5
t
RAC
= 60 ns
100
CAS before RAS
refresh current
I
CC5
RAS cycling
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 50 ns
150
mA
1, 2
t
RAC
= 60 ns
130
CAS before RAS
long refresh current
(4,096 cycles/128 ms,
only for the
μ
PD42S65165)
I
CC6
CAS before RAS refresh:
t
RC
= 31.3
μ
s
RAS, CAS:
V
CC
– 0.2 V
≤
V
IH
≤
V
IH (MAX.)
0 V
≤
V
IL
≤
0.2 V
t
RAS
≤
300 ns
500
μ
A
1, 2
Standby:
RAS, CAS
≥
V
CC
– 0.2 V
Address: V
IH
or V
IL
WE, OE: V
IH
I
O
= 0 mA
t
RAS
≤
1
μ
s
600
μ
A
1, 2
CAS before RAS
self refresh current
(only for the
μ
PD42S65165)
I
CC7
RAS, CAS:
t
RASS
= 5 ms
V
CC
– 0.2 V
≤
V
IH
≤
V
IH (MAX.)
0 V
≤
V
IL
≤
0.2 V
I
O
= 0 mA
400
μ
A
2
Input leakage current
I
I (L)
V
I
= 0 to 3.6 V
All other pins not under test = 0 V
–5
+5
μ
A
Output leakage current
I
O (L)
V
O
= 0 to 3.6 V
Output is disabled (Hi-Z)
–5
+5
μ
A
High level output voltage
V
OH
I
O
= –2.0 mA
2.4
V
Low level output voltage
V
OL
I
O
= +2.0 mA
0.4
V
Notes 1.
I
CC1
, I
CC3
, I
CC4
, I
CC5
and I
CC6
depend on cycle rates (t
RC
and t
HPC
).
2.
Specified values are obtained with outputs unloaded.
3.
I
CC1
and I
CC3
are measured assuming that address can be changed once or less during RAS
≤
V
IL (MAX.)
and
CAS
≥
V
IH (MIN.)
.
4.
I
CC3
is measured assuming that all column address inputs are held at either high or low.
5.
I
CC4
is measured assuming that all column address inputs are switched only once during each Hyper page
(EDO) cycle.
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