參數(shù)資料
型號(hào)： μPD4265165
廠(chǎng)商： NEC Corp.
英文描述： 64 M-Bit Dynamic Ram(64M 動(dòng)態(tài)存儲(chǔ)器)
中文描述： 64 m位動(dòng)態(tài)隨機(jī)存儲(chǔ)器（6400動(dòng)態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 535K
代理商： ΜPD4265165
μ
PD42S65165, 4265165
7
Cautions when using the hyper page mode (EDO)
1.
CAS access should be used to operate t
HPC
at the MIN. value.
2.
To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on the state of each signal.
(1) Both RAS and CAS are inactive (at the end of read cycle)
WE: inactive, OE: active
t
OFC
is effective when RAS is inactivated before CAS is inactivated.
t
OFR
is effective when CAS is inactivated before RAS is inactivated.
The slower of t
OFC
and t
OFR
becomes effective.
(2) Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ····· t
OEZ
is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either t
RRH
or t
RCH
must be met ····· t
WEZ
and t
WPZ
are effective.
The faster of t
OEZ
and t
WEZ
becomes effective.
The faster of (1) and (2) becomes effective.
3.
In read cycle, the effective specification depends on the state of CAS signal when controlling data output with
the OE signal.
(1) CAS: inactive, OE: active ····· t
CHO
is effective.
(2) CAS, OE: active ····· t
OCH
is effective.
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