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參數(shù)資料
| 型號(hào)： | μPD26401 |
| 廠商： | NEC Corp. |
| 英文描述： | 1M-Bit SRAM and 2M-Bit MASK ROM COMBO Chip(1M位SRAM 和2M位MASK ROM) |
| 中文描述： | 100萬位的SRAM和2M位掩膜ROM集成芯片（100萬位的SRAM和200萬位掩膜ROM） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 119K |
| 代理商： | ΜPD26401 |
14
μ
PD26401
RAM Write Cycle Timing Chart (/RAMCS Controlled)
t
AS
t
AW
High impedance
/WE (Input)
/RAMCS (Input)
A0 - A16 (Input)
I/O (Output)
/ROMCS (Input)
t
ROMRAM
t
RAMROM
t
WC
t
RAMCW
t
DH
t
DW
t
WP
t
WR
Data in
High impedance
Cautions 1. /RAMCS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in
phase with output signals.
Remarks 1.
Write operation is done during the overlap time of a low level /RAMCS and a low level /WE.
2.
/OE = High level.
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